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197d19d11c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35420 91177308-0d34-0410-b5e6-96231b3b80d8
68 lines
2.2 KiB
Plaintext
68 lines
2.2 KiB
Plaintext
//===---------------------------------------------------------------------===//
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Common register allocation / spilling problem:
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mul lr, r4, lr
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str lr, [sp, #+52]
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ldr lr, [r1, #+32]
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sxth r3, r3
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ldr r4, [sp, #+52]
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mla r4, r3, lr, r4
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can be:
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mul lr, r4, lr
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mov r4, lr
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str lr, [sp, #+52]
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ldr lr, [r1, #+32]
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sxth r3, r3
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mla r4, r3, lr, r4
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and then "merge" mul and mov:
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mul r4, r4, lr
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str lr, [sp, #+52]
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ldr lr, [r1, #+32]
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sxth r3, r3
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mla r4, r3, lr, r4
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It also increase the likelyhood the store may become dead.
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//===---------------------------------------------------------------------===//
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I think we should have a "hasSideEffects" flag (which is automatically set for
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stuff that "isLoad" "isCall" etc), and the remat pass should eventually be able
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to remat any instruction that has no side effects, if it can handle it and if
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profitable.
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For now, I'd suggest having the remat stuff work like this:
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1. I need to spill/reload this thing.
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2. Check to see if it has side effects.
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3. Check to see if it is simple enough: e.g. it only has one register
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destination and no register input.
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4. If so, clone the instruction, do the xform, etc.
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Advantages of this are:
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1. the .td file describes the behavior of the instructions, not the way the
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algorithm should work.
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2. as remat gets smarter in the future, we shouldn't have to be changing the .td
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files.
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3. it is easier to explain what the flag means in the .td file, because you
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don't have to pull in the explanation of how the current remat algo works.
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Some potential added complexities:
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1. Some instructions have to be glued to it's predecessor or successor. All of
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the PC relative instructions and condition code setting instruction. We could
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mark them as hasSideEffects, but that's not quite right. PC relative loads
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from constantpools can be remat'ed, for example. But it requires more than
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just cloning the instruction. Some instructions can be remat'ed but it
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expands to more than one instruction. But allocator will have to make a
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decision.
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4. As stated in 3, not as simple as cloning in some cases. The target will have
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to decide how to remat it. For example, an ARM 2-piece constant generation
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instruction is remat'ed as a load from constantpool.
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