Bill Wendling f6fb7ed53c We need to verify that the machine instruction we're using as a replacement for ... our current machine instruction defines a register with the same register class as what's being replaced. This showed up in the SPEC 403.gcc benchmark, where it would ICE because a tail call was expecting one register class but was given another. (The machine instruction verifier catches this situation.) <rdar://problem/10270968> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141830 91177308-0d34-0410-b5e6-96231b3b80d8		2011-10-12 23:03:40 +00:00
..
Analysis
Archive
Assembler
Bindings/Ocaml	ocaml bindings: add llvm_ipo based on IPO.h	2011-10-06 12:12:27 +00:00
Bitcode
BugPoint
CodeGen	We need to verify that the machine instruction we're using as a replacement for	2011-10-12 23:03:40 +00:00
DebugInfo	Add a new wrapper node for a DILexicalBlock that encapsulates it and a	2011-10-11 22:59:11 +00:00
ExecutionEngine
Feature
Integer
lib	s/tblgen/llvm-tblgen/g in a few missed places, including the tests	2011-10-06 13:39:59 +00:00
Linker
MC	Finish supporting cpp #file/line comments in assembler for error messages. So	2011-10-12 21:38:39 +00:00
Object	Add support for dumping section headers to llvm-objdump. This uses the same	2011-10-10 21:21:34 +00:00
Other
Scripts
TableGen	XFAIL tblgen tests on leak checkers.	2011-10-10 13:09:59 +00:00
Transforms	Removed colons from some target datalayout strings in test, since they don't match the required format.	2011-10-12 22:24:17 +00:00
Unit
Verifier
CMakeLists.txt
lit.cfg	s/tblgen/llvm-tblgen/g in a few missed places, including the tests	2011-10-06 13:39:59 +00:00
lit.site.cfg.in
Makefile
Makefile.tests
site.exp.in
TestRunner.sh