Bob Wilson f74a429816 Overhaul memory barriers in the ARM backend. Radar 8601999. ... There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8		2010-10-30 00:54:37 +00:00
..
Alpha
ARM	Teach machine cse to eliminate instructions with multiple physreg uses and defs. rdar://8610857.	2010-10-29 23:36:03 +00:00
Blackfin
CBackend
CellSPU	Change v64 datalayout in SPU.	2010-10-26 10:45:47 +00:00
CPP
Generic
MBlaze	Recommit 116986 with capitalization typo fixed.	2010-10-21 03:57:26 +00:00
Mips
MSP430
PowerPC	PowerPC varargs functions store live-in registers on the stack. Make sure we use	2010-10-11 20:43:09 +00:00
PTX	Add test case mov.ll for PTX device function	2010-10-19 13:21:51 +00:00
SPARC
SystemZ
Thumb	Overhaul memory barriers in the ARM backend. Radar 8601999.	2010-10-30 00:54:37 +00:00
Thumb2	Overhaul memory barriers in the ARM backend. Radar 8601999.	2010-10-30 00:54:37 +00:00
X86	Fix pastos in handling of AVX cvttsd2si, PR8491.	2010-10-28 00:35:54 +00:00
XCore
thumb2-mul.ll