llvm-6502/lib/CodeGen
2014-03-04 11:45:46 +00:00
..
AsmPrinter [Modules] Move ValueHandle into the IR library where Value itself lives. 2014-03-04 11:17:44 +00:00
SelectionDAG [Modules] Move CallSite into the IR library where it belogs. It is 2014-03-04 11:01:28 +00:00
AggressiveAntiDepBreaker.cpp Fix the aggressive anti-dep breaker's subregister definition handling 2014-02-26 20:20:30 +00:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp
AllocationOrder.h
Analysis.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
AntiDepBreaker.h
BasicTargetTransformInfo.cpp Switch all uses of LLVM_OVERRIDE to just use 'override' directly. 2014-03-02 09:09:27 +00:00
BranchFolding.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
BranchFolding.h
CalcSpillWeights.cpp [C++11] Replace llvm::tie with std::tie. 2014-03-02 13:30:33 +00:00
CallingConvLower.cpp
CMakeLists.txt [CodeGenPrepare] Move CodeGenPrepare into lib/CodeGen. 2014-02-22 00:07:45 +00:00
CodeGen.cpp [CodeGenPrepare] Move CodeGenPrepare into lib/CodeGen. 2014-02-22 00:07:45 +00:00
CodeGenPrepare.cpp [Modules] Move ValueMap to the IR library. While this class does not 2014-03-04 11:26:31 +00:00
CriticalAntiDepBreaker.cpp
CriticalAntiDepBreaker.h
DeadMachineInstructionElim.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
DFAPacketizer.cpp
DwarfEHPrepare.cpp [Modules] Move CallSite into the IR library where it belogs. It is 2014-03-04 11:01:28 +00:00
EarlyIfConversion.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
EdgeBundles.cpp
ErlangGC.cpp
ExecutionDepsFix.cpp
ExpandISelPseudos.cpp
ExpandPostRAPseudos.cpp
GCMetadata.cpp
GCMetadataPrinter.cpp
GCStrategy.cpp
IfConversion.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
InlineSpiller.cpp [C++11] Replace llvm::tie with std::tie. 2014-03-02 13:30:33 +00:00
InterferenceCache.cpp [C++11] Replace llvm::tie with std::tie. 2014-03-02 13:30:33 +00:00
InterferenceCache.h
IntrinsicLowering.cpp [Modules] Move CallSite into the IR library where it belogs. It is 2014-03-04 11:01:28 +00:00
JITCodeEmitter.cpp
LatencyPriorityQueue.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
LexicalScopes.cpp
LiveDebugVariables.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
LiveDebugVariables.h
LiveInterval.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
LiveIntervalAnalysis.cpp [C++11] Replace llvm::tie with std::tie. 2014-03-02 13:30:33 +00:00
LiveIntervalUnion.cpp
LivePhysRegs.cpp
LiveRangeCalc.cpp [C++11] Replace llvm::tie with std::tie. 2014-03-02 13:30:33 +00:00
LiveRangeCalc.h
LiveRangeEdit.cpp
LiveRegMatrix.cpp
LiveStackAnalysis.cpp
LiveVariables.cpp
LLVMBuild.txt
LLVMTargetMachine.cpp Make DisableIntegratedAS a TargetOption. 2014-02-21 03:13:54 +00:00
LocalStackSlotAllocation.cpp LocalStackSlotAllocation: Turn one-iteration loop into if. 2014-02-23 13:34:21 +00:00
MachineBasicBlock.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
MachineBlockFrequencyInfo.cpp
MachineBlockPlacement.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
MachineBranchProbabilityInfo.cpp
MachineCodeEmitter.cpp
MachineCopyPropagation.cpp
MachineCSE.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
MachineDominators.cpp
MachineFunction.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp
MachineInstr.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
MachineInstrBundle.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
MachineLICM.cpp
MachineLoopInfo.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
MachineModuleInfo.cpp
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachinePostDominators.cpp
MachineRegisterInfo.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
MachineScheduler.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
MachineSink.cpp Now that we have C++11, turn simple functors into lambdas and remove a ton of boilerplate. 2014-03-01 11:47:00 +00:00
MachineSSAUpdater.cpp
MachineTraceMetrics.cpp [C++11] Replace llvm::tie with std::tie. 2014-03-02 13:30:33 +00:00
MachineVerifier.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
Makefile
OcamlGC.cpp
OptimizePHIs.cpp
Passes.cpp
PeepholeOptimizer.cpp
PHIElimination.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
ProcessImplicitDefs.cpp
PrologEpilogInserter.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp
README.txt
RegAllocBase.cpp Fix typo 2014-02-22 19:31:28 +00:00
RegAllocBase.h
RegAllocBasic.cpp
RegAllocFast.cpp [C++11] Replace llvm::tie with std::tie. 2014-03-02 13:30:33 +00:00
RegAllocGreedy.cpp [C++11] Use std::tie to simplify compare operators. 2014-03-03 19:58:30 +00:00
RegAllocPBQP.cpp Re-apply r202551, which introduced new PBQP solver. 2014-03-03 18:50:05 +00:00
RegisterClassInfo.cpp
RegisterCoalescer.cpp [C++11] Replace llvm::tie with std::tie. 2014-03-02 13:30:33 +00:00
RegisterCoalescer.h
RegisterPressure.cpp
RegisterScavenging.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
ScheduleDAG.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
ScheduleDAGInstrs.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
ScheduleDAGPrinter.cpp
ScoreboardHazardRecognizer.cpp
ShadowStackGC.cpp [Modules] Move CallSite into the IR library where it belogs. It is 2014-03-04 11:01:28 +00:00
SjLjEHPrepare.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
SlotIndexes.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
Spiller.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
Spiller.h
SpillPlacement.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
SpillPlacement.h
SplitKit.cpp [C++11] Replace llvm::tie with std::tie. 2014-03-02 13:30:33 +00:00
SplitKit.h
StackColoring.cpp Now that we have C++11, turn simple functors into lambdas and remove a ton of boilerplate. 2014-03-01 11:47:00 +00:00
StackMapLivenessAnalysis.cpp
StackMaps.cpp [cleanup] Re-sort all the includes with utils/sort_includes.py. 2014-03-04 10:07:28 +00:00
StackProtector.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
StackSlotColoring.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
TailDuplication.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
TargetFrameLoweringImpl.cpp
TargetInstrInfo.cpp
TargetLoweringBase.cpp [C++11] Replace llvm::tie with std::tie. 2014-03-02 13:30:33 +00:00
TargetLoweringObjectFileImpl.cpp [cleanup] Re-sort all the includes with utils/sort_includes.py. 2014-03-04 10:07:28 +00:00
TargetOptionsImpl.cpp
TargetRegisterInfo.cpp
TargetSchedule.cpp
TwoAddressInstructionPass.cpp [C++11] Replace llvm::next and llvm::prior with std::next and std::prev. 2014-03-02 12:27:27 +00:00
UnreachableBlockElim.cpp [Modules] Move CFG.h to the IR library as it defines graph traits over 2014-03-04 11:45:46 +00:00
VirtRegMap.cpp [cleanup] Re-sort all the includes with utils/sort_includes.py. 2014-03-04 10:07:28 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.