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https://github.com/c64scene-ar/llvm-6502.git
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ebdeeab812
- Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134678 91177308-0d34-0410-b5e6-96231b3b80d8
50 lines
1.3 KiB
C++
50 lines
1.3 KiB
C++
//===-- ARMMCTargetDesc.h - ARM Target Descriptions -------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides ARM specific target descriptions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMMCTARGETDESC_H
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#define ARMMCTARGETDESC_H
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#include <string>
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namespace llvm {
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class MCSubtargetInfo;
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class Target;
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class StringRef;
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extern Target TheARMTarget, TheThumbTarget;
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namespace ARM_MC {
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std::string ParseARMTriple(StringRef TT);
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/// createARMMCSubtargetInfo - Create a ARM MCSubtargetInfo instance.
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/// This is exposed so Asm parser, etc. do not need to go through
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/// TargetRegistry.
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MCSubtargetInfo *createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
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StringRef FS);
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}
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} // End llvm namespace
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// Defines symbolic names for ARM registers. This defines a mapping from
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// register name to register number.
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//
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#define GET_REGINFO_ENUM
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#include "ARMGenRegisterInfo.inc"
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// Defines symbolic names for the ARM instructions.
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//
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#define GET_INSTRINFO_ENUM
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#include "ARMGenInstrInfo.inc"
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#endif
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