llvm-6502/test/CodeGen/AArch64/arm64-coalescing-MOVi32imm.ll
Weiming Zhao 8d5c72d513 This patch eanble register coalescing to coalesce the following:
%vreg2<def> = MOVi32imm 1; GPR32:%vreg2
  %W1<def> = COPY %vreg2; GPR32:%vreg2
into:
  %W1<def> = MOVi32imm 1
Patched by Lawrence Hu (lawrence@codeaurora.org)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243033 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-23 19:24:53 +00:00

19 lines
380 B
LLVM

; RUN: llc < %s | FileCheck %s
; CHECK: orr w0, wzr, #0x1
; CHECK-NEXT : bl foo
; CHECK-NEXT : orr w0, wzr, #0x1
; CHECK-NEXT : bl foo
target triple = "aarch64--linux-android"
declare i32 @foo(i32)
; Function Attrs: nounwind uwtable
define i32 @main() {
entry:
%call = tail call i32 @foo(i32 1)
%call1 = tail call i32 @foo(i32 1)
ret i32 0
}