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f7ab3a84b3
Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188995 91177308-0d34-0410-b5e6-96231b3b80d8
15 lines
409 B
LLVM
15 lines
409 B
LLVM
; RUN: llc < %s -mcpu=cortex-a8 -march=arm -asm-verbose=false | FileCheck %s
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define zeroext i1 @test0(i32 %x) nounwind {
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; CHECK-LABEL: test0:
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; CHECK-NEXT: add [[REG:(r[0-9]+)|(lr)]], r0, #1
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; CHECK-NEXT: mov r0, #0
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; CHECK-NEXT: cmp [[REG]], #1
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; CHECK-NEXT: movwhi r0, #1
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; CHECK-NEXT: bx lr
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%cmp1 = icmp ne i32 %x, -1
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%not.cmp = icmp ne i32 %x, 0
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%.cmp1 = and i1 %cmp1, %not.cmp
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ret i1 %.cmp1
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}
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