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https://github.com/c64scene-ar/llvm-6502.git
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b1ebd6981f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157433 91177308-0d34-0410-b5e6-96231b3b80d8
109 lines
4.3 KiB
TableGen
109 lines
4.3 KiB
TableGen
//===-- NVPTXRegisterInfo.td - NVPTX Register defs ---------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the PTX register file
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//===----------------------------------------------------------------------===//
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class NVPTXReg<string n> : Register<n> {
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let Namespace = "NVPTX";
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}
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class NVPTXRegClass<list<ValueType> regTypes, int alignment, dag regList>
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: RegisterClass <"NVPTX", regTypes, alignment, regList>;
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//===----------------------------------------------------------------------===//
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// Registers
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//===----------------------------------------------------------------------===//
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// Special Registers used as stack pointer
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def VRFrame : NVPTXReg<"%SP">;
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def VRFrameLocal : NVPTXReg<"%SPL">;
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// Special Registers used as the stack
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def VRDepot : NVPTXReg<"%Depot">;
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foreach i = 0-395 in {
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def P#i : NVPTXReg<"%p"#i>; // Predicate
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def RC#i : NVPTXReg<"%rc"#i>; // 8-bit
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def RS#i : NVPTXReg<"%rs"#i>; // 16-bit
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def R#i : NVPTXReg<"%r"#i>; // 32-bit
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def RL#i : NVPTXReg<"%rl"#i>; // 64-bit
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def F#i : NVPTXReg<"%f"#i>; // 32-bit float
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def FL#i : NVPTXReg<"%fl"#i>; // 64-bit float
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// Vectors
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foreach s = [ "2b8", "2b16", "2b32", "2b64", "4b8", "4b16", "4b32" ] in
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def v#s#_#i : NVPTXReg<"%v"#s#"_"#i>;
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// Arguments
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def ia#i : NVPTXReg<"%ia"#i>;
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def la#i : NVPTXReg<"%la"#i>;
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def fa#i : NVPTXReg<"%fa"#i>;
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def da#i : NVPTXReg<"%da"#i>;
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}
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//===----------------------------------------------------------------------===//
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// Register classes
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//===----------------------------------------------------------------------===//
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def Int1Regs : NVPTXRegClass<[i1], 8, (add (sequence "P%u", 0, 395))>;
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def Int8Regs : NVPTXRegClass<[i8], 8, (add (sequence "RC%u", 0, 395))>;
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def Int16Regs : NVPTXRegClass<[i16], 16, (add (sequence "RS%u", 0, 395))>;
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def Int32Regs : NVPTXRegClass<[i32], 32, (add (sequence "R%u", 0, 395))>;
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def Int64Regs : NVPTXRegClass<[i64], 64, (add (sequence "RL%u", 0, 395))>;
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def Float32Regs : NVPTXRegClass<[f32], 32, (add (sequence "F%u", 0, 395))>;
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def Float64Regs : NVPTXRegClass<[f64], 64, (add (sequence "FL%u", 0, 395))>;
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def Int32ArgRegs : NVPTXRegClass<[i32], 32, (add (sequence "ia%u", 0, 395))>;
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def Int64ArgRegs : NVPTXRegClass<[i64], 64, (add (sequence "la%u", 0, 395))>;
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def Float32ArgRegs : NVPTXRegClass<[f32], 32, (add (sequence "fa%u", 0, 395))>;
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def Float64ArgRegs : NVPTXRegClass<[f64], 64, (add (sequence "da%u", 0, 395))>;
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// Read NVPTXRegisterInfo.cpp to see how VRFrame and VRDepot are used.
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def SpecialRegs : NVPTXRegClass<[i32], 32, (add VRFrame, VRDepot)>;
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class NVPTXVecRegClass<list<ValueType> regTypes, int alignment, dag regList,
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NVPTXRegClass sClass,
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int e,
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string n>
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: NVPTXRegClass<regTypes, alignment, regList>
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{
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NVPTXRegClass scalarClass=sClass;
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int elems=e;
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string name=n;
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}
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def V2F32Regs
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: NVPTXVecRegClass<[v2f32], 64, (add (sequence "v2b32_%u", 0, 395)),
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Float32Regs, 2, ".v2.f32">;
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def V4F32Regs
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: NVPTXVecRegClass<[v4f32], 128, (add (sequence "v4b32_%u", 0, 395)),
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Float32Regs, 4, ".v4.f32">;
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def V2I32Regs
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: NVPTXVecRegClass<[v2i32], 64, (add (sequence "v2b32_%u", 0, 395)),
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Int32Regs, 2, ".v2.u32">;
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def V4I32Regs
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: NVPTXVecRegClass<[v4i32], 128, (add (sequence "v4b32_%u", 0, 395)),
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Int32Regs, 4, ".v4.u32">;
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def V2F64Regs
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: NVPTXVecRegClass<[v2f64], 128, (add (sequence "v2b64_%u", 0, 395)),
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Float64Regs, 2, ".v2.f64">;
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def V2I64Regs
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: NVPTXVecRegClass<[v2i64], 128, (add (sequence "v2b64_%u", 0, 395)),
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Int64Regs, 2, ".v2.u64">;
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def V2I16Regs
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: NVPTXVecRegClass<[v2i16], 32, (add (sequence "v2b16_%u", 0, 395)),
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Int16Regs, 2, ".v2.u16">;
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def V4I16Regs
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: NVPTXVecRegClass<[v4i16], 64, (add (sequence "v4b16_%u", 0, 395)),
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Int16Regs, 4, ".v4.u16">;
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def V2I8Regs
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: NVPTXVecRegClass<[v2i8], 16, (add (sequence "v2b8_%u", 0, 395)),
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Int8Regs, 2, ".v2.u8">;
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def V4I8Regs
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: NVPTXVecRegClass<[v4i8], 32, (add (sequence "v4b8_%u", 0, 395)),
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Int8Regs, 4, ".v4.u8">;
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