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c356e565a6
Also use distinct names for the three types of SetMachineOperand to avoid painful overloading problems and errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1904 91177308-0d34-0410-b5e6-96231b3b80d8
185 lines
4.7 KiB
C++
185 lines
4.7 KiB
C++
// $Id$
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//***************************************************************************
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// File:
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// MachineInstr.cpp
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//
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// Purpose:
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//
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//
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// Strategy:
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//
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// History:
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// 7/2/01 - Vikram Adve - Created
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//**************************************************************************/
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Value.h"
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#include <iostream>
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using std::cerr;
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//************************ Class Implementations **************************/
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// Constructor for instructions with fixed #operands (nearly all)
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MachineInstr::MachineInstr(MachineOpCode _opCode,
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OpCodeMask _opCodeMask)
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: opCode(_opCode),
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opCodeMask(_opCodeMask),
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operands(TargetInstrDescriptors[_opCode].numOperands)
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{
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assert(TargetInstrDescriptors[_opCode].numOperands >= 0);
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}
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// Constructor for instructions with variable #operands
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MachineInstr::MachineInstr(MachineOpCode _opCode,
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unsigned numOperands,
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OpCodeMask _opCodeMask)
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: opCode(_opCode),
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opCodeMask(_opCodeMask),
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operands(numOperands)
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{
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}
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void
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MachineInstr::SetMachineOperandVal(unsigned int i,
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MachineOperand::MachineOperandType operandType,
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Value* _val, bool isdef=false)
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{
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assert(i < operands.size());
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operands[i].Initialize(operandType, _val);
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operands[i].isDef = isdef ||
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TargetInstrDescriptors[opCode].resultPos == (int) i;
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}
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void
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MachineInstr::SetMachineOperandConst(unsigned int i,
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MachineOperand::MachineOperandType operandType,
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int64_t intValue)
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{
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assert(i < operands.size());
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assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
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"immed. constant cannot be defined");
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operands[i].InitializeConst(operandType, intValue);
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operands[i].isDef = false;
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}
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void
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MachineInstr::SetMachineOperandReg(unsigned int i,
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int regNum,
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bool isdef=false,
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bool isCCReg=false)
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{
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assert(i < operands.size());
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operands[i].InitializeReg(regNum, isCCReg);
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operands[i].isDef = isdef ||
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TargetInstrDescriptors[opCode].resultPos == (int) i;
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}
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void
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MachineInstr::dump(unsigned int indent) const
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{
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for (unsigned i=0; i < indent; i++)
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cerr << " ";
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cerr << *this;
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}
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std::ostream &operator<<(std::ostream& os, const MachineInstr& minstr)
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{
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os << TargetInstrDescriptors[minstr.opCode].opCodeString;
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for (unsigned i=0, N=minstr.getNumOperands(); i < N; i++) {
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os << "\t" << minstr.getOperand(i);
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if( minstr.getOperand(i).opIsDef() )
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os << "*";
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}
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#undef DEBUG_VAL_OP_ITERATOR
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#ifdef DEBUG_VAL_OP_ITERATOR
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os << "\n\tValue operands are: ";
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for (MachineInstr::val_const_op_iterator vo(&minstr); ! vo.done(); ++vo)
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{
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const Value* val = *vo;
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os << val << (vo.isDef()? "(def), " : ", ");
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}
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#endif
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#if 1
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// code for printing implict references
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unsigned NumOfImpRefs = minstr.getNumImplicitRefs();
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if( NumOfImpRefs > 0 ) {
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os << "\tImplicit:";
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for(unsigned z=0; z < NumOfImpRefs; z++) {
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os << minstr.getImplicitRef(z);
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if( minstr.implicitRefIsDefined(z)) os << "*";
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os << "\t";
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}
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}
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#endif
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return os << "\n";
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}
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static inline std::ostream &OutputOperand(std::ostream &os,
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const MachineOperand &mop)
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{
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Value* val;
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switch (mop.getOperandType())
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{
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case MachineOperand::MO_CCRegister:
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case MachineOperand::MO_VirtualRegister:
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val = mop.getVRegValue();
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os << "(val ";
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if (val && val->hasName())
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os << val->getName();
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else
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os << val;
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return os << ")";
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case MachineOperand::MO_MachineRegister:
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return os << "(" << mop.getMachineRegNum() << ")";
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default:
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assert(0 && "Unknown operand type");
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return os;
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}
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}
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std::ostream &operator<<(std::ostream &os, const MachineOperand &mop)
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{
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switch(mop.opType)
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{
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case MachineOperand::MO_VirtualRegister:
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case MachineOperand::MO_MachineRegister:
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os << "%reg";
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return OutputOperand(os, mop);
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case MachineOperand::MO_CCRegister:
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os << "%ccreg";
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return OutputOperand(os, mop);
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case MachineOperand::MO_SignExtendedImmed:
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return os << (long)mop.immedVal;
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case MachineOperand::MO_UnextendedImmed:
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return os << (long)mop.immedVal;
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case MachineOperand::MO_PCRelativeDisp:
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{
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const Value* opVal = mop.getVRegValue();
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bool isLabel = isa<Method>(opVal) || isa<BasicBlock>(opVal);
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os << "%disp(" << (isLabel? "label " : "addr-of-val ");
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if (opVal->hasName())
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os << opVal->getName();
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else
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os << opVal;
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return os << ")";
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}
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default:
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assert(0 && "Unrecognized operand type");
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break;
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}
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return os;
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}
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