Saleem Abdulrasool f7f22a64df [ARM] check bitwidth in PerformORCombine ... When simplifying a (or (and B A) (and C ~A)) to a (VBSL A B C) ensure that the bitwidth of the second operands to both ands match before comparing the negation of the values. Split the check of the value of the second operands to the ands. Move the cast and variable declaration slightly higher to make it slightly easier to follow. Bug-Id: 16700 Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187404 91177308-0d34-0410-b5e6-96231b3b80d8		2013-07-30 04:43:08 +00:00
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AArch64
ARM	[ARM] check bitwidth in PerformORCombine	2013-07-30 04:43:08 +00:00
CPP
Generic
Hexagon	Debug Info Verifier: verify SPs in llvm.dbg.sp.	2013-07-27 01:26:08 +00:00
Inputs	Debug Info Verifier: verify SPs in llvm.dbg.sp.	2013-07-27 01:26:08 +00:00
Mips	[mips] Implement llvm.trap intrinsic.	2013-07-26 20:58:55 +00:00
MSP430
NVPTX	Add a target legalize hook for SplitVectorOperand (again)	2013-07-26 13:28:29 +00:00
PowerPC
R600	[R600] Replicate old DAGCombiner behavior in target specific DAG combine.	2013-07-30 00:27:16 +00:00
SI
SPARC
SystemZ
Thumb	Debug Info: update testing cases to pass verifier.	2013-07-29 18:12:58 +00:00
Thumb2
X86	[DAGCombiner] insert_vector_elt: Avoid building a vector twice.	2013-07-30 00:24:09 +00:00
XCore