mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
167 lines
6.6 KiB
LLVM
167 lines
6.6 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck --check-prefix=SI --check-prefix=BOTH %s
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; RUN: llc -march=r600 -mcpu=bonaire -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=BOTH %s
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; BOTH-LABEL: {{^}}local_i32_load
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; BOTH: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}} offset:28 [M0]
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; BOTH: buffer_store_dword [[REG]],
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define void @local_i32_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounwind {
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%gep = getelementptr i32 addrspace(3)* %in, i32 7
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%val = load i32 addrspace(3)* %gep, align 4
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store i32 %val, i32 addrspace(1)* %out, align 4
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ret void
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}
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; BOTH-LABEL: {{^}}local_i32_load_0_offset
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; BOTH: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}} [M0]
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; BOTH: buffer_store_dword [[REG]],
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define void @local_i32_load_0_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounwind {
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%val = load i32 addrspace(3)* %in, align 4
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store i32 %val, i32 addrspace(1)* %out, align 4
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ret void
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}
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; BOTH-LABEL: {{^}}local_i8_load_i16_max_offset:
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; BOTH-NOT: ADD
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; BOTH: ds_read_u8 [[REG:v[0-9]+]], {{v[0-9]+}} offset:65535 [M0]
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; BOTH: buffer_store_byte [[REG]],
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define void @local_i8_load_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %in) nounwind {
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%gep = getelementptr i8 addrspace(3)* %in, i32 65535
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%val = load i8 addrspace(3)* %gep, align 4
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store i8 %val, i8 addrspace(1)* %out, align 4
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ret void
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}
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; BOTH-LABEL: {{^}}local_i8_load_over_i16_max_offset:
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; The LDS offset will be 65536 bytes, which is larger than the size of LDS on
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; SI, which is why it is being OR'd with the base pointer.
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; SI: s_or_b32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
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; CI: s_add_i32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
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; BOTH: v_mov_b32_e32 [[VREGADDR:v[0-9]+]], [[ADDR]]
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; BOTH: ds_read_u8 [[REG:v[0-9]+]], [[VREGADDR]] [M0]
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; BOTH: buffer_store_byte [[REG]],
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define void @local_i8_load_over_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %in) nounwind {
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%gep = getelementptr i8 addrspace(3)* %in, i32 65536
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%val = load i8 addrspace(3)* %gep, align 4
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store i8 %val, i8 addrspace(1)* %out, align 4
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ret void
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}
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; BOTH-LABEL: {{^}}local_i64_load:
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; BOTH-NOT: ADD
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; BOTH: ds_read_b64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}} offset:56 [M0]
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; BOTH: buffer_store_dwordx2 [[REG]],
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define void @local_i64_load(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounwind {
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%gep = getelementptr i64 addrspace(3)* %in, i32 7
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%val = load i64 addrspace(3)* %gep, align 8
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store i64 %val, i64 addrspace(1)* %out, align 8
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ret void
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}
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; BOTH-LABEL: {{^}}local_i64_load_0_offset
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; BOTH: ds_read_b64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} [M0]
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; BOTH: buffer_store_dwordx2 [[REG]],
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define void @local_i64_load_0_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounwind {
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%val = load i64 addrspace(3)* %in, align 8
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store i64 %val, i64 addrspace(1)* %out, align 8
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ret void
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}
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; BOTH-LABEL: {{^}}local_f64_load:
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; BOTH-NOT: ADD
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; BOTH: ds_read_b64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}} offset:56 [M0]
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; BOTH: buffer_store_dwordx2 [[REG]],
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define void @local_f64_load(double addrspace(1)* %out, double addrspace(3)* %in) nounwind {
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%gep = getelementptr double addrspace(3)* %in, i32 7
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%val = load double addrspace(3)* %gep, align 8
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store double %val, double addrspace(1)* %out, align 8
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ret void
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}
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; BOTH-LABEL: {{^}}local_f64_load_0_offset
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; BOTH: ds_read_b64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} [M0]
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; BOTH: buffer_store_dwordx2 [[REG]],
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define void @local_f64_load_0_offset(double addrspace(1)* %out, double addrspace(3)* %in) nounwind {
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%val = load double addrspace(3)* %in, align 8
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store double %val, double addrspace(1)* %out, align 8
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ret void
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}
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; BOTH-LABEL: {{^}}local_i64_store:
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; BOTH-NOT: ADD
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; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:56 [M0]
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define void @local_i64_store(i64 addrspace(3)* %out) nounwind {
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%gep = getelementptr i64 addrspace(3)* %out, i32 7
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store i64 5678, i64 addrspace(3)* %gep, align 8
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ret void
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}
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; BOTH-LABEL: {{^}}local_i64_store_0_offset:
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; BOTH-NOT: ADD
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; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0]
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define void @local_i64_store_0_offset(i64 addrspace(3)* %out) nounwind {
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store i64 1234, i64 addrspace(3)* %out, align 8
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ret void
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}
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; BOTH-LABEL: {{^}}local_f64_store:
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; BOTH-NOT: ADD
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; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:56 [M0]
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define void @local_f64_store(double addrspace(3)* %out) nounwind {
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%gep = getelementptr double addrspace(3)* %out, i32 7
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store double 16.0, double addrspace(3)* %gep, align 8
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ret void
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}
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; BOTH-LABEL: {{^}}local_f64_store_0_offset
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; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0]
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define void @local_f64_store_0_offset(double addrspace(3)* %out) nounwind {
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store double 20.0, double addrspace(3)* %out, align 8
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ret void
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}
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; BOTH-LABEL: {{^}}local_v2i64_store:
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; BOTH-NOT: ADD
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; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:112 [M0]
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; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:120 [M0]
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; BOTH: s_endpgm
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define void @local_v2i64_store(<2 x i64> addrspace(3)* %out) nounwind {
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%gep = getelementptr <2 x i64> addrspace(3)* %out, i32 7
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store <2 x i64> <i64 5678, i64 5678>, <2 x i64> addrspace(3)* %gep, align 16
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ret void
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}
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; BOTH-LABEL: {{^}}local_v2i64_store_0_offset:
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; BOTH-NOT: ADD
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; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0]
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; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8 [M0]
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; BOTH: s_endpgm
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define void @local_v2i64_store_0_offset(<2 x i64> addrspace(3)* %out) nounwind {
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store <2 x i64> <i64 1234, i64 1234>, <2 x i64> addrspace(3)* %out, align 16
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ret void
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}
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; BOTH-LABEL: {{^}}local_v4i64_store:
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; BOTH-NOT: ADD
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; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:224 [M0]
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; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:232 [M0]
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; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:240 [M0]
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; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:248 [M0]
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; BOTH: s_endpgm
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define void @local_v4i64_store(<4 x i64> addrspace(3)* %out) nounwind {
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%gep = getelementptr <4 x i64> addrspace(3)* %out, i32 7
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store <4 x i64> <i64 5678, i64 5678, i64 5678, i64 5678>, <4 x i64> addrspace(3)* %gep, align 16
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ret void
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}
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; BOTH-LABEL: {{^}}local_v4i64_store_0_offset:
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; BOTH-NOT: ADD
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; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0]
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; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8 [M0]
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; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16 [M0]
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; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24 [M0]
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; BOTH: s_endpgm
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define void @local_v4i64_store_0_offset(<4 x i64> addrspace(3)* %out) nounwind {
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store <4 x i64> <i64 1234, i64 1234, i64 1234, i64 1234>, <4 x i64> addrspace(3)* %out, align 16
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ret void
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}
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