mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
80 lines
2.1 KiB
LLVM
80 lines
2.1 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}test_a:
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; EG-NOT: CND
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; EG: SET{{[NEQGTL]+}}_DX10
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define void @test_a(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp olt float %in, 0.000000e+00
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%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
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%2 = fsub float -0.000000e+00, %1
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%3 = fptosi float %2 to i32
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%4 = bitcast i32 %3 to float
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%5 = bitcast float %4 to i32
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%6 = icmp ne i32 %5, 0
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br i1 %6, label %IF, label %ENDIF
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IF:
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%7 = getelementptr i32 addrspace(1)* %out, i32 1
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store i32 0, i32 addrspace(1)* %7
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br label %ENDIF
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ENDIF:
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store i32 0, i32 addrspace(1)* %out
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ret void
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}
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; Same as test_a, but the branch labels are swapped to produce the inverse cc
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; for the icmp instruction
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; EG-LABEL: {{^}}test_b:
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; EG: SET{{[GTEQN]+}}_DX10
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; EG-NEXT: PRED_
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; EG-NEXT: ALU clause starting
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define void @test_b(i32 addrspace(1)* %out, float %in) {
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entry:
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%0 = fcmp olt float %in, 0.0
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%1 = select i1 %0, float 1.000000e+00, float 0.000000e+00
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%2 = fsub float -0.000000e+00, %1
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%3 = fptosi float %2 to i32
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%4 = bitcast i32 %3 to float
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%5 = bitcast float %4 to i32
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%6 = icmp ne i32 %5, 0
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br i1 %6, label %ENDIF, label %IF
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IF:
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%7 = getelementptr i32 addrspace(1)* %out, i32 1
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store i32 0, i32 addrspace(1)* %7
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br label %ENDIF
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ENDIF:
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store i32 0, i32 addrspace(1)* %out
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ret void
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}
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; Test a CND*_INT instruction with float true/false values
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; EG-LABEL: {{^}}test_c:
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; EG: CND{{[GTE]+}}_INT
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define void @test_c(float addrspace(1)* %out, i32 %in) {
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entry:
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%0 = icmp sgt i32 %in, 0
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%1 = select i1 %0, float 2.0, float 3.0
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store float %1, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}selectcc_bool:
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; SI: v_cmp_ne_i32
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; SI-NEXT: v_cndmask_b32_e64
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; SI-NOT: cmp
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; SI-NOT: cndmask
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define void @selectcc_bool(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind {
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%icmp0 = icmp ne i32 %a, %b
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%ext = select i1 %icmp0, i32 -1, i32 0
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store i32 %ext, i32 addrspace(1)* %out
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ret void
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}
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