mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
68 lines
2.4 KiB
LLVM
68 lines
2.4 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s
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define void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) {
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; SI-LABEL: {{^}}trunc_i64_to_i32_store:
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; SI: s_load_dword [[SLOAD:s[0-9]+]], s[0:1], 0xb
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; SI: v_mov_b32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]]
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; SI: buffer_store_dword [[VLOAD]]
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; EG-LABEL: {{^}}trunc_i64_to_i32_store:
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; EG: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
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; EG: LSHR
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; EG-NEXT: 2(
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%result = trunc i64 %in to i32 store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}trunc_load_shl_i64:
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; SI-DAG: s_load_dwordx2
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; SI-DAG: s_load_dword [[SREG:s[0-9]+]],
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; SI: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2
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; SI: v_mov_b32_e32 [[VSHL:v[0-9]+]], [[SHL]]
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; SI: buffer_store_dword [[VSHL]],
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define void @trunc_load_shl_i64(i32 addrspace(1)* %out, i64 %a) {
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%b = shl i64 %a, 2
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%result = trunc i64 %b to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}trunc_shl_i64:
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; SI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
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; SI: s_lshl_b64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2
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; SI: s_add_u32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]],
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; SI: s_addc_u32
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; SI: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]]
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; SI: buffer_store_dword v[[LO_VREG]],
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define void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64 %a) {
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%aa = add i64 %a, 234 ; Prevent shrinking store.
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%b = shl i64 %aa, 2
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%result = trunc i64 %b to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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store i64 %b, i64 addrspace(1)* %out2, align 8 ; Prevent reducing ops to 32-bits
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ret void
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}
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; SI-LABEL: {{^}}trunc_i32_to_i1:
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; SI: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
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; SI: v_cmp_eq_i32
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define void @trunc_i32_to_i1(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) {
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%a = load i32 addrspace(1)* %ptr, align 4
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%trunc = trunc i32 %a to i1
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%result = select i1 %trunc, i32 1, i32 0
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}sgpr_trunc_i32_to_i1:
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; SI: v_and_b32_e64 v{{[0-9]+}}, 1, s{{[0-9]+}}
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; SI: v_cmp_eq_i32
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define void @sgpr_trunc_i32_to_i1(i32 addrspace(1)* %out, i32 %a) {
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%trunc = trunc i32 %a to i1
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%result = select i1 %trunc, i32 1, i32 0
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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