mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7b3cde87f1
This patch corresponds to review: http://reviews.llvm.org/D10638 This is the back end portion of patch http://reviews.llvm.org/D10637 It just adds the code gen and intrinsic functions necessary to support that patch to the back end. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240820 91177308-0d34-0410-b5e6-96231b3b80d8
166 lines
5.5 KiB
LLVM
166 lines
5.5 KiB
LLVM
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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@vda = common global <2 x double> zeroinitializer, align 16
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@vdb = common global <2 x double> zeroinitializer, align 16
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@vdr = common global <2 x double> zeroinitializer, align 16
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@vfa = common global <4 x float> zeroinitializer, align 16
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@vfb = common global <4 x float> zeroinitializer, align 16
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@vfr = common global <4 x float> zeroinitializer, align 16
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@vbllr = common global <2 x i64> zeroinitializer, align 16
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@vbir = common global <4 x i32> zeroinitializer, align 16
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@vblla = common global <2 x i64> zeroinitializer, align 16
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@vbllb = common global <2 x i64> zeroinitializer, align 16
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@vbia = common global <4 x i32> zeroinitializer, align 16
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@vbib = common global <4 x i32> zeroinitializer, align 16
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; Function Attrs: nounwind
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define void @test1() {
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entry:
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%0 = load <2 x double>, <2 x double>* @vda, align 16
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%1 = load <2 x double>, <2 x double>* @vdb, align 16
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%2 = call <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double> %0, <2 x double> %1)
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store <2 x double> %2, <2 x double>* @vdr, align 16
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ret void
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; CHECK-LABEL: @test1
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; CHECK: xvdivdp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test2() {
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entry:
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%0 = load <4 x float>, <4 x float>* @vfa, align 16
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%1 = load <4 x float>, <4 x float>* @vfb, align 16
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%2 = call <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float> %0, <4 x float> %1)
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store <4 x float> %2, <4 x float>* @vfr, align 16
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ret void
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; CHECK-LABEL: @test2
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; CHECK: xvdivsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test3() {
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entry:
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%0 = load <2 x double>, <2 x double>* @vda, align 16
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%1 = load <2 x double>, <2 x double>* @vda, align 16
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%2 = call <2 x double> @llvm.ceil.v2f64(<2 x double> %1)
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store <2 x double> %2, <2 x double>* @vdr, align 16
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ret void
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; CHECK-LABEL: @test3
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; CHECK: xvrdpip {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test4() {
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entry:
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%0 = load <4 x float>, <4 x float>* @vfa, align 16
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%1 = load <4 x float>, <4 x float>* @vfa, align 16
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%2 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %1)
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store <4 x float> %2, <4 x float>* @vfr, align 16
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ret void
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; CHECK-LABEL: @test4
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; CHECK: xvrspip {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test5() {
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entry:
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%0 = load <2 x double>, <2 x double>* @vda, align 16
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%1 = load <2 x double>, <2 x double>* @vdb, align 16
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%2 = call <2 x i64> @llvm.ppc.vsx.xvcmpeqdp(<2 x double> %0, <2 x double> %1)
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store <2 x i64> %2, <2 x i64>* @vbllr, align 16
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ret void
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; CHECK-LABEL: @test5
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; CHECK: xvcmpeqdp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test6() {
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entry:
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%0 = load <4 x float>, <4 x float>* @vfa, align 16
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%1 = load <4 x float>, <4 x float>* @vfb, align 16
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%2 = call <4 x i32> @llvm.ppc.vsx.xvcmpeqsp(<4 x float> %0, <4 x float> %1)
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store <4 x i32> %2, <4 x i32>* @vbir, align 16
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ret void
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; CHECK-LABEL: @test6
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; CHECK: xvcmpeqsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test7() {
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entry:
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%0 = load <2 x double>, <2 x double>* @vda, align 16
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%1 = load <2 x double>, <2 x double>* @vdb, align 16
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%2 = call <2 x i64> @llvm.ppc.vsx.xvcmpgedp(<2 x double> %0, <2 x double> %1)
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store <2 x i64> %2, <2 x i64>* @vbllr, align 16
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ret void
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; CHECK-LABEL: @test7
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; CHECK: xvcmpgedp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test8() {
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entry:
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%0 = load <4 x float>, <4 x float>* @vfa, align 16
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%1 = load <4 x float>, <4 x float>* @vfb, align 16
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%2 = call <4 x i32> @llvm.ppc.vsx.xvcmpgesp(<4 x float> %0, <4 x float> %1)
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store <4 x i32> %2, <4 x i32>* @vbir, align 16
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ret void
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; CHECK-LABEL: @test8
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; CHECK: xvcmpgesp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test9() {
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entry:
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%0 = load <2 x double>, <2 x double>* @vda, align 16
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%1 = load <2 x double>, <2 x double>* @vdb, align 16
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%2 = call <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double> %0, <2 x double> %1)
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store <2 x i64> %2, <2 x i64>* @vbllr, align 16
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ret void
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; CHECK-LABEL: @test9
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; CHECK: xvcmpgtdp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind
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define void @test10() {
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entry:
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%0 = load <4 x float>, <4 x float>* @vfa, align 16
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%1 = load <4 x float>, <4 x float>* @vfb, align 16
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%2 = call <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float> %0, <4 x float> %1)
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store <4 x i32> %2, <4 x i32>* @vbir, align 16
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ret void
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; CHECK-LABEL: @test10
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; CHECK: xvcmpgtsp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind readnone
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declare <2 x double> @llvm.ceil.v2f64(<2 x double>)
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; Function Attrs: nounwind readnone
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declare <4 x float> @llvm.ceil.v4f32(<4 x float>)
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; Function Attrs: nounwind readnone
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declare <2 x double> @llvm.ppc.vsx.xvdivdp(<2 x double>, <2 x double>)
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; Function Attrs: nounwind readnone
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declare <4 x float> @llvm.ppc.vsx.xvdivsp(<4 x float>, <4 x float>)
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; Function Attrs: nounwind readnone
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declare <2 x i64> @llvm.ppc.vsx.xvcmpeqdp(<2 x double>, <2 x double>)
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.ppc.vsx.xvcmpeqsp(<4 x float>, <4 x float>)
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; Function Attrs: nounwind readnone
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declare <2 x i64> @llvm.ppc.vsx.xvcmpgedp(<2 x double>, <2 x double>)
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.ppc.vsx.xvcmpgesp(<4 x float>, <4 x float>)
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; Function Attrs: nounwind readnone
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declare <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double>, <2 x double>)
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float>, <4 x float>)
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