mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-20 10:30:03 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
120 lines
4.2 KiB
LLVM
120 lines
4.2 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
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define <2 x i32> @vrecpei32(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: vrecpei32:
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;CHECK: vrecpe.u32
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <4 x i32> @vrecpeQi32(<4 x i32>* %A) nounwind {
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;CHECK-LABEL: vrecpeQi32:
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;CHECK: vrecpe.u32
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %tmp1)
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ret <4 x i32> %tmp2
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}
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define <2 x float> @vrecpef32(<2 x float>* %A) nounwind {
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;CHECK-LABEL: vrecpef32:
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;CHECK: vrecpe.f32
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%tmp1 = load <2 x float>, <2 x float>* %A
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%tmp2 = call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> %tmp1)
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ret <2 x float> %tmp2
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}
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define <4 x float> @vrecpeQf32(<4 x float>* %A) nounwind {
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;CHECK-LABEL: vrecpeQf32:
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;CHECK: vrecpe.f32
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%tmp1 = load <4 x float>, <4 x float>* %A
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%tmp2 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp1)
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ret <4 x float> %tmp2
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}
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declare <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32>) nounwind readnone
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declare <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
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define <2 x float> @vrecpsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vrecpsf32:
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;CHECK: vrecps.f32
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%tmp1 = load <2 x float>, <2 x float>* %A
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%tmp2 = load <2 x float>, <2 x float>* %B
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%tmp3 = call <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
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ret <2 x float> %tmp3
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}
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define <4 x float> @vrecpsQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
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;CHECK-LABEL: vrecpsQf32:
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;CHECK: vrecps.f32
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%tmp1 = load <4 x float>, <4 x float>* %A
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%tmp2 = load <4 x float>, <4 x float>* %B
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%tmp3 = call <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
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ret <4 x float> %tmp3
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}
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declare <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float>, <2 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
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define <2 x i32> @vrsqrtei32(<2 x i32>* %A) nounwind {
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;CHECK-LABEL: vrsqrtei32:
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;CHECK: vrsqrte.u32
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%tmp1 = load <2 x i32>, <2 x i32>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <4 x i32> @vrsqrteQi32(<4 x i32>* %A) nounwind {
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;CHECK-LABEL: vrsqrteQi32:
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;CHECK: vrsqrte.u32
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%tmp1 = load <4 x i32>, <4 x i32>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1)
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ret <4 x i32> %tmp2
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}
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define <2 x float> @vrsqrtef32(<2 x float>* %A) nounwind {
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;CHECK-LABEL: vrsqrtef32:
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;CHECK: vrsqrte.f32
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%tmp1 = load <2 x float>, <2 x float>* %A
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%tmp2 = call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %tmp1)
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ret <2 x float> %tmp2
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}
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define <4 x float> @vrsqrteQf32(<4 x float>* %A) nounwind {
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;CHECK-LABEL: vrsqrteQf32:
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;CHECK: vrsqrte.f32
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%tmp1 = load <4 x float>, <4 x float>* %A
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%tmp2 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %tmp1)
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ret <4 x float> %tmp2
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}
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declare <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32>) nounwind readnone
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declare <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
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define <2 x float> @vrsqrtsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vrsqrtsf32:
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;CHECK: vrsqrts.f32
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%tmp1 = load <2 x float>, <2 x float>* %A
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%tmp2 = load <2 x float>, <2 x float>* %B
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%tmp3 = call <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)
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ret <2 x float> %tmp3
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}
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define <4 x float> @vrsqrtsQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
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;CHECK-LABEL: vrsqrtsQf32:
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;CHECK: vrsqrts.f32
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%tmp1 = load <4 x float>, <4 x float>* %A
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%tmp2 = load <4 x float>, <4 x float>* %B
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%tmp3 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2)
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ret <4 x float> %tmp3
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}
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declare <2 x float> @llvm.arm.neon.vrsqrts.v2f32(<2 x float>, <2 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float>, <4 x float>) nounwind readnone
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