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https://github.com/c64scene-ar/llvm-6502.git
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225ca9cdd7
important. - Cleanup in the Subtarget info with addition of new features, not all support yet, but they allow the future inclusion of features easier. Among new features, we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit integer and float registers, allegrex vector FPU (VFPU), single float only support. - TargetMachine now detects allegrex core. - Added allegrex (Mips32r2) sext_inreg instructions. - *Added Float Point Instructions*, handling single float only, and aliased accesses for 32-bit FPUs. - Some cleanup in FP instruction formats and FP register classes. - Calling conventions improved to support mips 32-bit EABI. - Added Asm Printer support for fp cond codes. - Added support for sret copy to a return register. - EABI support added into LowerCALL and FORMAL_ARGS. - MipsFunctionInfo now keeps a virtual register per function to track the sret on function entry until function ret. - MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...), FP cond codes mapping and initial FP Branch Analysis. - Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond, FPCmp - MipsTargetLowering : handling different FP classes, Allegrex support, sret return copy, no homing location within EABI, non 32-bit stack objects arguments, and asm constraint for float. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53146 91177308-0d34-0410-b5e6-96231b3b80d8
236 lines
8.5 KiB
C++
236 lines
8.5 KiB
C++
//===- MipsRegisterInfo.td - Mips Register defs -----------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the MIPS register file
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//===----------------------------------------------------------------------===//
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// We have banks of 32 registers each.
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class MipsReg<string n> : Register<n> {
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field bits<5> Num;
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let Namespace = "Mips";
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}
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// Mips CPU Registers
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class MipsGPRReg<bits<5> num, string n> : MipsReg<n> {
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let Num = num;
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}
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// Mips 32-bit FPU Registers
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class FPR<bits<5> num, string n> : MipsReg<n> {
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let Num = num;
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}
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// Mips 64-bit (aliased) FPU Registers
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class AFPR<bits<5> num, string n, list<Register> aliases> : MipsReg<n> {
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let Num = num;
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let Aliases = aliases;
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}
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//===----------------------------------------------------------------------===//
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// Registers
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//===----------------------------------------------------------------------===//
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let Namespace = "Mips" in {
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// General Purpose Registers
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def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>;
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def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;
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def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
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def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
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def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[5]>;
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def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
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def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
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def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
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def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
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def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
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def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>;
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def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>;
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def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>;
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def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>;
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def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>;
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def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>;
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def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>;
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def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>;
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def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>;
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def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>;
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def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>;
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def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>;
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def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>;
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def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>;
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def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>;
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def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>;
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def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;
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def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>;
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def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<[28]>;
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def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>;
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def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>;
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def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>;
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/// Mips Single point precision FPU Registers
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def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>;
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def F1 : FPR< 1, "F1">, DwarfRegNum<[33]>;
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def F2 : FPR< 2, "F2">, DwarfRegNum<[34]>;
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def F3 : FPR< 3, "F3">, DwarfRegNum<[35]>;
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def F4 : FPR< 4, "F4">, DwarfRegNum<[36]>;
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def F5 : FPR< 5, "F5">, DwarfRegNum<[37]>;
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def F6 : FPR< 6, "F6">, DwarfRegNum<[38]>;
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def F7 : FPR< 7, "F7">, DwarfRegNum<[39]>;
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def F8 : FPR< 8, "F8">, DwarfRegNum<[40]>;
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def F9 : FPR< 9, "F9">, DwarfRegNum<[41]>;
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def F10 : FPR<10, "F10">, DwarfRegNum<[42]>;
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def F11 : FPR<11, "F11">, DwarfRegNum<[43]>;
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def F12 : FPR<12, "F12">, DwarfRegNum<[44]>;
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def F13 : FPR<13, "F13">, DwarfRegNum<[45]>;
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def F14 : FPR<14, "F14">, DwarfRegNum<[46]>;
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def F15 : FPR<15, "F15">, DwarfRegNum<[47]>;
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def F16 : FPR<16, "F16">, DwarfRegNum<[48]>;
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def F17 : FPR<17, "F17">, DwarfRegNum<[49]>;
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def F18 : FPR<18, "F18">, DwarfRegNum<[50]>;
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def F19 : FPR<19, "F19">, DwarfRegNum<[51]>;
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def F20 : FPR<20, "F20">, DwarfRegNum<[52]>;
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def F21 : FPR<21, "F21">, DwarfRegNum<[53]>;
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def F22 : FPR<22, "F22">, DwarfRegNum<[54]>;
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def F23 : FPR<23, "F23">, DwarfRegNum<[55]>;
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def F24 : FPR<24, "F24">, DwarfRegNum<[56]>;
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def F25 : FPR<25, "F25">, DwarfRegNum<[57]>;
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def F26 : FPR<26, "F26">, DwarfRegNum<[58]>;
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def F27 : FPR<27, "F27">, DwarfRegNum<[59]>;
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def F28 : FPR<28, "F28">, DwarfRegNum<[60]>;
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def F29 : FPR<29, "F29">, DwarfRegNum<[61]>;
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def F30 : FPR<30, "F30">, DwarfRegNum<[62]>;
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def F31 : FPR<31, "F31">, DwarfRegNum<[63]>;
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/// Mips Double point precision FPU Registers (aliased
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/// with the single precision to hold 64 bit values)
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def D0 : AFPR< 0, "F0", [F0, F1]>, DwarfRegNum<[32]>;
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def D1 : AFPR< 2, "F2", [F2, F3]>, DwarfRegNum<[34]>;
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def D2 : AFPR< 4, "F4", [F4, F5]>, DwarfRegNum<[36]>;
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def D3 : AFPR< 6, "F6", [F6, F7]>, DwarfRegNum<[38]>;
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def D4 : AFPR< 8, "F8", [F8, F9]>, DwarfRegNum<[40]>;
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def D5 : AFPR<10, "F10", [F10, F11]>, DwarfRegNum<[42]>;
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def D6 : AFPR<12, "F12", [F12, F13]>, DwarfRegNum<[44]>;
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def D7 : AFPR<14, "F14", [F14, F15]>, DwarfRegNum<[46]>;
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def D8 : AFPR<16, "F16", [F16, F17]>, DwarfRegNum<[48]>;
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def D9 : AFPR<18, "F18", [F18, F19]>, DwarfRegNum<[50]>;
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def D10 : AFPR<20, "F20", [F20, F21]>, DwarfRegNum<[52]>;
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def D11 : AFPR<22, "F22", [F22, F23]>, DwarfRegNum<[54]>;
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def D12 : AFPR<24, "F24", [F24, F25]>, DwarfRegNum<[56]>;
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def D13 : AFPR<26, "F26", [F26, F27]>, DwarfRegNum<[58]>;
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def D14 : AFPR<28, "F28", [F28, F29]>, DwarfRegNum<[60]>;
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def D15 : AFPR<30, "F30", [F30, F31]>, DwarfRegNum<[62]>;
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// Status flags register
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def FCR31 : Register<"FCR31">;
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}
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//===----------------------------------------------------------------------===//
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// Register Classes
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//===----------------------------------------------------------------------===//
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def CPURegs : RegisterClass<"Mips", [i32], 32,
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// Return Values and Arguments
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[V0, V1, A0, A1, A2, A3,
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// Not preserved across procedure calls
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T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
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// Callee save
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S0, S1, S2, S3, S4, S5, S6, S7,
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// Reserved
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ZERO, AT, K0, K1, GP, SP, FP, RA]>
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{
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let MethodProtos = [{
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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CPURegsClass::iterator
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CPURegsClass::allocation_order_end(const MachineFunction &MF) const {
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// The last 8 registers on the list above are reserved
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return end()-8;
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}
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}];
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}
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// * 64bit fp:
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// - FGR64 = 32 64-bit registers (default mode)
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// - AFGR32/AFGR64 = 16 even 32-bit registers (32-bit compatible mode) for
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// single and double access.
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// * 32bit fp:
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// - AFGR32/AFGR64 = 16 even 32-bit registers - single and double
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// - FGR32 = 32 32-bit registers (within single-only mode)
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def FGR32 : RegisterClass<"Mips", [f32], 32,
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// Return Values and Arguments
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[F0, F1, F2, F3, F12, F13, F14, F15,
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// Not preserved across procedure calls
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F4, F5, F6, F7, F8, F9, F10, F11, F16, F17, F18, F19,
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// Callee save
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F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
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// Reserved
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F31]>
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{
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let MethodProtos = [{
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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FGR32Class::iterator
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FGR32Class::allocation_order_end(const MachineFunction &MF) const {
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// The last register on the list above is reserved
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return end()-1;
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}
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}];
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}
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def AFGR32 : RegisterClass<"Mips", [f32], 32,
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// Return Values and Arguments
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[F0, F2, F12, F14,
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// Not preserved across procedure calls
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F4, F6, F8, F10, F16, F18,
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// Callee save
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F20, F22, F24, F26, F28, F30,
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// Reserved
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F31]>
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{
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let MethodProtos = [{
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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AFGR32Class::iterator
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AFGR32Class::allocation_order_end(const MachineFunction &MF) const {
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// The last register on the list above is reserved
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return end()-1;
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}
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}];
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}
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def AFGR64 : RegisterClass<"Mips", [f64], 64,
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// Return Values and Arguments
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[D0, D1, D6, D7,
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// Not preserved across procedure calls
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D2, D3, D4, D5, D8, D9,
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// Callee save
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D10, D11, D12, D13, D14,
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// Reserved
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D15]>
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{
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let MethodProtos = [{
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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AFGR64Class::iterator
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AFGR64Class::allocation_order_end(const MachineFunction &MF) const {
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// The last register on the list above is reserved
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return end()-1;
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}
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}];
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}
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def CCR : RegisterClass<"Mips", [i32], 32, [FCR31]> {
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let CopyCost = -1; // Don't allow copying of status registers.
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}
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