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d93969c32a
This field specifies registers that are preserved across function calls, but that should not be included in the generates SaveList array. This can be used ot generate regmasks for architectures that save registers through other means, like SPARC's register windows. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189084 91177308-0d34-0410-b5e6-96231b3b80d8
137 lines
4.8 KiB
C++
137 lines
4.8 KiB
C++
//===-- SparcRegisterInfo.cpp - SPARC Register Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SPARC implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcRegisterInfo.h"
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#include "Sparc.h"
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#include "SparcMachineFunctionInfo.h"
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#include "SparcSubtarget.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define GET_REGINFO_TARGET_DESC
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#include "SparcGenRegisterInfo.inc"
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using namespace llvm;
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static cl::opt<bool>
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ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
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cl::desc("Reserve application registers (%g2-%g4)"));
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SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st)
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: SparcGenRegisterInfo(SP::I7), Subtarget(st) {
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}
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const uint16_t* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
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const {
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return CSR_SaveList;
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}
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const uint32_t*
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SparcRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
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return CSR_RegMask;
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}
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BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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// FIXME: G1 reserved for now for large imm generation by frame code.
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Reserved.set(SP::G1);
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// G1-G4 can be used in applications.
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if (ReserveAppRegisters) {
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Reserved.set(SP::G2);
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Reserved.set(SP::G3);
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Reserved.set(SP::G4);
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}
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// G5 is not reserved in 64 bit mode.
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if (!Subtarget.is64Bit())
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Reserved.set(SP::G5);
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Reserved.set(SP::O6);
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Reserved.set(SP::I6);
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Reserved.set(SP::I7);
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Reserved.set(SP::G0);
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Reserved.set(SP::G6);
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Reserved.set(SP::G7);
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return Reserved;
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}
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const TargetRegisterClass*
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SparcRegisterInfo::getPointerRegClass(const MachineFunction &MF,
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unsigned Kind) const {
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return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
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}
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void
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SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(SPAdj == 0 && "Unexpected");
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MachineInstr &MI = *II;
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DebugLoc dl = MI.getDebugLoc();
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int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
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// Addressable stack objects are accessed using neg. offsets from %fp
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MachineFunction &MF = *MI.getParent()->getParent();
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int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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MI.getOperand(FIOperandNum + 1).getImm() +
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Subtarget.getStackPointerBias();
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SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
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unsigned FramePtr = SP::I6;
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if (FuncInfo->isLeafProc()) {
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// Use %sp and adjust offset if needed.
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FramePtr = SP::O6;
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int stackSize = MF.getFrameInfo()->getStackSize();
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Offset += (stackSize) ? Subtarget.getAdjustedFrameSize(stackSize) : 0 ;
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}
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// Replace frame index with a frame pointer reference.
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if (Offset >= -4096 && Offset <= 4095) {
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// If the offset is small enough to fit in the immediate field, directly
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// encode it.
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MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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} else {
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// Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
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// scavenge a register here instead of reserving G1 all of the time.
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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unsigned OffHi = (unsigned)Offset >> 10U;
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
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// Emit G1 = G1 + I6
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
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.addReg(FramePtr);
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// Insert: G1+%lo(offset) into the user.
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MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset & ((1 << 10)-1));
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}
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}
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unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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return SP::I6;
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}
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unsigned SparcRegisterInfo::getEHExceptionRegister() const {
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llvm_unreachable("What is the exception register");
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}
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unsigned SparcRegisterInfo::getEHHandlerRegister() const {
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llvm_unreachable("What is the exception handler register");
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}
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