Reid Kleckner f89d9b1c75 Add an IR-to-IR test for dwarf EH preparation using opt ... This tests the simple resume instruction elimination logic that we have before making some changes to it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229768 91177308-0d34-0410-b5e6-96231b3b80d8		2015-02-18 23:17:41 +00:00
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AArch64
ARM	[ARM] Add missing M/R class CPUs	2015-02-18 10:33:30 +00:00
BPF
CPP
Generic
Hexagon
Inputs
Mips	[mips][microMIPS] Make usage of ADDU16 and SUBU16 by code generator	2015-02-18 17:33:56 +00:00
MSP430
NVPTX
PowerPC	This patch adds the VSX logical instructions introduced in the Power ISA 2.07. It also removes the added complexity that favors VMX versions of the three instructions.	2015-02-18 16:21:46 +00:00
R600	R600/SI: Add missing offset operand to buffer bothen	2015-02-18 02:04:38 +00:00
SPARC
SystemZ	[SystemZ] Support all TLS access models - CodeGen part	2015-02-18 09:13:27 +00:00
Thumb
Thumb2
X86	Add an IR-to-IR test for dwarf EH preparation using opt	2015-02-18 23:17:41 +00:00
XCore