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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97578 91177308-0d34-0410-b5e6-96231b3b80d8
188 lines
6.6 KiB
C++
188 lines
6.6 KiB
C++
//===- DeadMachineInstructionElim.cpp - Remove dead machine instructions --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is an extremely simple MachineInstr-level dead-code-elimination pass.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "codegen-dce"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Pass.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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STATISTIC(NumDeletes, "Number of dead instructions deleted");
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namespace {
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class DeadMachineInstructionElim : public MachineFunctionPass {
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virtual bool runOnMachineFunction(MachineFunction &MF);
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const TargetRegisterInfo *TRI;
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const MachineRegisterInfo *MRI;
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const TargetInstrInfo *TII;
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BitVector LivePhysRegs;
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public:
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static char ID; // Pass identification, replacement for typeid
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DeadMachineInstructionElim() : MachineFunctionPass(&ID) {}
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private:
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bool isDead(const MachineInstr *MI) const;
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};
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}
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char DeadMachineInstructionElim::ID = 0;
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static RegisterPass<DeadMachineInstructionElim>
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Y("dead-mi-elimination",
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"Remove dead machine instructions");
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FunctionPass *llvm::createDeadMachineInstructionElimPass() {
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return new DeadMachineInstructionElim();
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}
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bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
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// Don't delete instructions with side effects.
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bool SawStore = false;
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if (!MI->isSafeToMove(TII, 0, SawStore) && !MI->isPHI())
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return false;
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// Examine each operand.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isDef()) {
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unsigned Reg = MO.getReg();
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if (TargetRegisterInfo::isPhysicalRegister(Reg) ?
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LivePhysRegs[Reg] : !MRI->use_nodbg_empty(Reg)) {
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// This def has a non-debug use. Don't delete the instruction!
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return false;
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}
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}
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}
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// If there are no defs with uses, the instruction is dead.
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return true;
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}
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bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
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bool AnyChanges = false;
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MRI = &MF.getRegInfo();
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TRI = MF.getTarget().getRegisterInfo();
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TII = MF.getTarget().getInstrInfo();
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// Compute a bitvector to represent all non-allocatable physregs.
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BitVector NonAllocatableRegs = TRI->getAllocatableSet(MF);
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NonAllocatableRegs.flip();
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// Loop over all instructions in all blocks, from bottom to top, so that it's
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// more likely that chains of dependent but ultimately dead instructions will
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// be cleaned up.
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for (MachineFunction::reverse_iterator I = MF.rbegin(), E = MF.rend();
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I != E; ++I) {
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MachineBasicBlock *MBB = &*I;
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// Start out assuming that all non-allocatable registers are live
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// out of this block.
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LivePhysRegs = NonAllocatableRegs;
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// Also add any explicit live-out physregs for this block.
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if (!MBB->empty() && MBB->back().getDesc().isReturn())
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for (MachineRegisterInfo::liveout_iterator LOI = MRI->liveout_begin(),
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LOE = MRI->liveout_end(); LOI != LOE; ++LOI) {
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unsigned Reg = *LOI;
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if (TargetRegisterInfo::isPhysicalRegister(Reg))
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LivePhysRegs.set(Reg);
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}
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// Now scan the instructions and delete dead ones, tracking physreg
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// liveness as we go.
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for (MachineBasicBlock::reverse_iterator MII = MBB->rbegin(),
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MIE = MBB->rend(); MII != MIE; ) {
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MachineInstr *MI = &*MII;
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// If the instruction is dead, delete it!
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if (isDead(MI)) {
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DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI);
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// It is possible that some DBG_VALUE instructions refer to this
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// instruction. Examine each def operand for such references;
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// if found, mark the DBG_VALUE as undef (but don't delete it).
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isDef())
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continue;
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unsigned Reg = MO.getReg();
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if (!TargetRegisterInfo::isVirtualRegister(Reg))
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continue;
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MachineRegisterInfo::use_iterator nextI;
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for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
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E = MRI->use_end(); I!=E; I=nextI) {
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nextI = llvm::next(I); // I is invalidated by the setReg
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MachineOperand& Use = I.getOperand();
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MachineInstr *UseMI = Use.getParent();
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if (UseMI==MI)
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continue;
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assert(Use.isDebug());
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UseMI->getOperand(0).setReg(0U);
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}
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}
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AnyChanges = true;
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MI->eraseFromParent();
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++NumDeletes;
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MIE = MBB->rend();
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// MII is now pointing to the next instruction to process,
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// so don't increment it.
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continue;
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}
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// Record the physreg defs.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isDef()) {
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unsigned Reg = MO.getReg();
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if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
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LivePhysRegs.reset(Reg);
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// Check the subreg set, not the alias set, because a def
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// of a super-register may still be partially live after
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// this def.
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for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
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*SubRegs; ++SubRegs)
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LivePhysRegs.reset(*SubRegs);
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}
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}
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}
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// Record the physreg uses, after the defs, in case a physreg is
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// both defined and used in the same instruction.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.isUse()) {
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unsigned Reg = MO.getReg();
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if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
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LivePhysRegs.set(Reg);
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for (const unsigned *AliasSet = TRI->getAliasSet(Reg);
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*AliasSet; ++AliasSet)
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LivePhysRegs.set(*AliasSet);
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}
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}
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}
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// We didn't delete the current instruction, so increment MII to
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// the next one.
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++MII;
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}
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}
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LivePhysRegs.clear();
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return AnyChanges;
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}
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