mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
26d628d6ce
Summary: Currently fast-isel-abort will only abort for regular instructions, and just warn for function calls, terminators, function arguments. There is already fast-isel-abort-args but nothing for calls and terminators. This change turns the fast-isel-abort options into an integer option, so that multiple levels of strictness can be defined. This will help no being surprised when the "abort" option indeed does not abort, and enables the possibility to write test that verifies that no intrinsics are forgotten by fast-isel. Reviewers: resistor, echristo Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D7941 From: Mehdi Amini <mehdi.amini@apple.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230775 91177308-0d34-0410-b5e6-96231b3b80d8
101 lines
2.5 KiB
LLVM
101 lines
2.5 KiB
LLVM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
|
|
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
|
|
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
|
|
; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv8-apple-ios | FileCheck %s --check-prefix=THUMB
|
|
|
|
define i32 @t1(i1 %c) nounwind readnone {
|
|
entry:
|
|
; ARM: t1
|
|
; ARM: movw r{{[1-9]}}, #10
|
|
; ARM: cmp r0, #0
|
|
; ARM: moveq r{{[1-9]}}, #20
|
|
; ARM: mov r0, r{{[1-9]}}
|
|
; THUMB: t1
|
|
; THUMB: movs r{{[1-9]}}, #10
|
|
; THUMB: cmp r0, #0
|
|
; THUMB: it eq
|
|
; THUMB: moveq r{{[1-9]}}, #20
|
|
; THUMB: mov r0, r{{[1-9]}}
|
|
%0 = select i1 %c, i32 10, i32 20
|
|
ret i32 %0
|
|
}
|
|
|
|
define i32 @t2(i1 %c, i32 %a) nounwind readnone {
|
|
entry:
|
|
; ARM: t2
|
|
; ARM: cmp r0, #0
|
|
; ARM: moveq r{{[1-9]}}, #20
|
|
; ARM: mov r0, r{{[1-9]}}
|
|
; THUMB: t2
|
|
; THUMB: cmp r0, #0
|
|
; THUMB: it eq
|
|
; THUMB: moveq r{{[1-9]}}, #20
|
|
; THUMB: mov r0, r{{[1-9]}}
|
|
%0 = select i1 %c, i32 %a, i32 20
|
|
ret i32 %0
|
|
}
|
|
|
|
define i32 @t3(i1 %c, i32 %a, i32 %b) nounwind readnone {
|
|
entry:
|
|
; ARM: t3
|
|
; ARM: cmp r0, #0
|
|
; ARM: movne r2, r1
|
|
; ARM: add r0, r2, r1
|
|
; THUMB: t3
|
|
; THUMB: cmp r0, #0
|
|
; THUMB: it ne
|
|
; THUMB: movne r2, r1
|
|
; THUMB: add.w r0, r2, r1
|
|
%0 = select i1 %c, i32 %a, i32 %b
|
|
%1 = add i32 %0, %a
|
|
ret i32 %1
|
|
}
|
|
|
|
define i32 @t4(i1 %c) nounwind readnone {
|
|
entry:
|
|
; ARM: t4
|
|
; ARM: mvn r{{[1-9]}}, #9
|
|
; ARM: cmp r0, #0
|
|
; ARM: mvneq r{{[1-9]}}, #0
|
|
; ARM: mov r0, r{{[1-9]}}
|
|
; THUMB-LABEL: t4
|
|
; THUMB: mvn [[REG:r[1-9]+]], #9
|
|
; THUMB: cmp r0, #0
|
|
; THUMB: it eq
|
|
; THUMB: mvneq [[REG]], #0
|
|
; THUMB: mov r0, [[REG]]
|
|
%0 = select i1 %c, i32 -10, i32 -1
|
|
ret i32 %0
|
|
}
|
|
|
|
define i32 @t5(i1 %c, i32 %a) nounwind readnone {
|
|
entry:
|
|
; ARM: t5
|
|
; ARM: cmp r0, #0
|
|
; ARM: mvneq r{{[1-9]}}, #1
|
|
; ARM: mov r0, r{{[1-9]}}
|
|
; THUMB: t5
|
|
; THUMB: cmp r0, #0
|
|
; THUMB: it eq
|
|
; THUMB: mvneq r{{[1-9]}}, #1
|
|
; THUMB: mov r0, r{{[1-9]}}
|
|
%0 = select i1 %c, i32 %a, i32 -2
|
|
ret i32 %0
|
|
}
|
|
|
|
; Check one large negative immediates.
|
|
define i32 @t6(i1 %c, i32 %a) nounwind readnone {
|
|
entry:
|
|
; ARM: t6
|
|
; ARM: cmp r0, #0
|
|
; ARM: mvneq r{{[1-9]}}, #978944
|
|
; ARM: mov r0, r{{[1-9]}}
|
|
; THUMB: t6
|
|
; THUMB: cmp r0, #0
|
|
; THUMB: it eq
|
|
; THUMB: mvneq r{{[1-9]}}, #978944
|
|
; THUMB: mov r0, r{{[1-9]}}
|
|
%0 = select i1 %c, i32 %a, i32 -978945
|
|
ret i32 %0
|
|
}
|