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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106705 91177308-0d34-0410-b5e6-96231b3b80d8
4040 lines
191 KiB
TableGen
4040 lines
191 KiB
TableGen
//====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 SSE instruction set, defining the instructions,
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// and properties of the instructions which are needed for code generation,
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// machine code emission, and analysis.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// SSE specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
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SDTCisFP<0>, SDTCisInt<2> ]>;
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def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
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SDTCisFP<1>, SDTCisVT<3, i8>]>;
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def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
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def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
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def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]>;
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def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
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def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
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def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
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def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
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def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
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def X86pshufb : SDNode<"X86ISD::PSHUFB",
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SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
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SDTCisSameAs<0,2>]>>;
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def X86pextrb : SDNode<"X86ISD::PEXTRB",
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SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
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def X86pextrw : SDNode<"X86ISD::PEXTRW",
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SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
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def X86pinsrb : SDNode<"X86ISD::PINSRB",
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SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
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SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
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def X86pinsrw : SDNode<"X86ISD::PINSRW",
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SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
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SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
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def X86insrtps : SDNode<"X86ISD::INSERTPS",
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SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
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SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
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def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
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SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
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def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
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[SDNPHasChain, SDNPMayLoad]>;
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def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
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def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
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def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
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def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
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def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
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def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
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def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
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def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
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def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
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def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
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def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
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def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
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def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
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SDTCisVT<1, v4f32>,
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SDTCisVT<2, v4f32>]>;
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def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
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//===----------------------------------------------------------------------===//
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// SSE Complex Patterns
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//===----------------------------------------------------------------------===//
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// These are 'extloads' from a scalar to the low element of a vector, zeroing
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// the top elements. These are used for the SSE 'ss' and 'sd' instruction
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// forms.
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def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
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[SDNPHasChain, SDNPMayLoad]>;
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def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
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[SDNPHasChain, SDNPMayLoad]>;
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def ssmem : Operand<v4f32> {
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let PrintMethod = "printf32mem";
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let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
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let ParserMatchClass = X86MemAsmOperand;
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}
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def sdmem : Operand<v2f64> {
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let PrintMethod = "printf64mem";
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let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
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let ParserMatchClass = X86MemAsmOperand;
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}
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//===----------------------------------------------------------------------===//
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// SSE pattern fragments
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//===----------------------------------------------------------------------===//
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def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
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def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
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def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
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def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
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// Like 'store', but always requires vector alignment.
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def alignedstore : PatFrag<(ops node:$val, node:$ptr),
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(store node:$val, node:$ptr), [{
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return cast<StoreSDNode>(N)->getAlignment() >= 16;
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}]>;
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// Like 'load', but always requires vector alignment.
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def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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return cast<LoadSDNode>(N)->getAlignment() >= 16;
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}]>;
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def alignedloadfsf32 : PatFrag<(ops node:$ptr),
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(f32 (alignedload node:$ptr))>;
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def alignedloadfsf64 : PatFrag<(ops node:$ptr),
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(f64 (alignedload node:$ptr))>;
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def alignedloadv4f32 : PatFrag<(ops node:$ptr),
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(v4f32 (alignedload node:$ptr))>;
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def alignedloadv2f64 : PatFrag<(ops node:$ptr),
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(v2f64 (alignedload node:$ptr))>;
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def alignedloadv4i32 : PatFrag<(ops node:$ptr),
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(v4i32 (alignedload node:$ptr))>;
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def alignedloadv2i64 : PatFrag<(ops node:$ptr),
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(v2i64 (alignedload node:$ptr))>;
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// Like 'load', but uses special alignment checks suitable for use in
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// memory operands in most SSE instructions, which are required to
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// be naturally aligned on some targets but not on others. If the subtarget
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// allows unaligned accesses, match any load, though this may require
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// setting a feature bit in the processor (on startup, for example).
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// Opteron 10h and later implement such a feature.
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def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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return Subtarget->hasVectorUAMem()
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|| cast<LoadSDNode>(N)->getAlignment() >= 16;
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}]>;
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def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
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def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
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def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
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def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
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def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
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def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
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def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
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// SSSE3 uses MMX registers for some instructions. They aren't aligned on a
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// 16-byte boundary.
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// FIXME: 8 byte alignment for mmx reads is not required
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def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
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return cast<LoadSDNode>(N)->getAlignment() >= 8;
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}]>;
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def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
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def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
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def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
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def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
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// MOVNT Support
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// Like 'store', but requires the non-temporal bit to be set
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def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
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(st node:$val, node:$ptr), [{
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if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
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return ST->isNonTemporal();
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return false;
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}]>;
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def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
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(st node:$val, node:$ptr), [{
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if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
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return ST->isNonTemporal() && !ST->isTruncatingStore() &&
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ST->getAddressingMode() == ISD::UNINDEXED &&
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ST->getAlignment() >= 16;
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return false;
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}]>;
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def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
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(st node:$val, node:$ptr), [{
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if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
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return ST->isNonTemporal() &&
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ST->getAlignment() < 16;
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return false;
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}]>;
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def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
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def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
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def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
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def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
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def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
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def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
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def vzmovl_v2i64 : PatFrag<(ops node:$src),
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(bitconvert (v2i64 (X86vzmovl
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(v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
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def vzmovl_v4i32 : PatFrag<(ops node:$src),
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(bitconvert (v4i32 (X86vzmovl
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(v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
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def vzload_v2i64 : PatFrag<(ops node:$src),
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(bitconvert (v2i64 (X86vzload node:$src)))>;
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def fp32imm0 : PatLeaf<(f32 fpimm), [{
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return N->isExactlyValue(+0.0);
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}]>;
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// BYTE_imm - Transform bit immediates into byte immediates.
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def BYTE_imm : SDNodeXForm<imm, [{
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// Transformation function: imm >> 3
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return getI32Imm(N->getZExtValue() >> 3);
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}]>;
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// SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
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// SHUFP* etc. imm.
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def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
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return getI8Imm(X86::getShuffleSHUFImmediate(N));
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}]>;
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// SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
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// PSHUFHW imm.
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def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
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return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
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}]>;
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// SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
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// PSHUFLW imm.
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def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
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return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
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}]>;
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// SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
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// a PALIGNR imm.
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def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
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return getI8Imm(X86::getShufflePALIGNRImmediate(N));
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}]>;
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def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
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return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
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}]>;
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def movddup : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
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}]>;
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def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
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}]>;
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def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
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}]>;
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def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
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}]>;
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def movlp : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
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}]>;
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def movl : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
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}]>;
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def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
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}]>;
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def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
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}]>;
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def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
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}]>;
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def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
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}]>;
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def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
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}]>;
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def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
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}]>;
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def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
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}], SHUFFLE_get_shuf_imm>;
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def shufp : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
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}], SHUFFLE_get_shuf_imm>;
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def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
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}], SHUFFLE_get_pshufhw_imm>;
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def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
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}], SHUFFLE_get_pshuflw_imm>;
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def palign : PatFrag<(ops node:$lhs, node:$rhs),
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(vector_shuffle node:$lhs, node:$rhs), [{
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return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
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}], SHUFFLE_get_palign_imm>;
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//===----------------------------------------------------------------------===//
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// SSE scalar FP Instructions
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//===----------------------------------------------------------------------===//
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// CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
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// instruction selection into a branch sequence.
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let Uses = [EFLAGS], usesCustomInserter = 1 in {
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def CMOV_FR32 : I<0, Pseudo,
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(outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
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"#CMOV_FR32 PSEUDO!",
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[(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
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EFLAGS))]>;
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def CMOV_FR64 : I<0, Pseudo,
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(outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
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"#CMOV_FR64 PSEUDO!",
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[(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
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EFLAGS))]>;
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def CMOV_V4F32 : I<0, Pseudo,
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(outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
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"#CMOV_V4F32 PSEUDO!",
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[(set VR128:$dst,
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(v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
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EFLAGS)))]>;
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def CMOV_V2F64 : I<0, Pseudo,
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(outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
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"#CMOV_V2F64 PSEUDO!",
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[(set VR128:$dst,
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(v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
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EFLAGS)))]>;
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def CMOV_V2I64 : I<0, Pseudo,
|
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(outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
|
|
"#CMOV_V2I64 PSEUDO!",
|
|
[(set VR128:$dst,
|
|
(v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
|
|
EFLAGS)))]>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SSE 1 & 2 Instructions Classes
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
|
|
multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
|
RegisterClass RC, X86MemOperand x86memop> {
|
|
let isCommutable = 1 in {
|
|
def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
|
|
OpcodeStr, [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
|
|
}
|
|
def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
|
|
OpcodeStr, [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
|
|
}
|
|
|
|
/// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
|
|
multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
|
|
string asm, string SSEVer, string FPSizeStr,
|
|
Operand memopr, ComplexPattern mem_cpat> {
|
|
def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
|
|
asm, [(set RC:$dst, (
|
|
!nameconcat<Intrinsic>("int_x86_sse",
|
|
!strconcat(SSEVer, !strconcat("_",
|
|
!strconcat(OpcodeStr, FPSizeStr))))
|
|
RC:$src1, RC:$src2))]>;
|
|
def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
|
|
asm, [(set RC:$dst, (
|
|
!nameconcat<Intrinsic>("int_x86_sse",
|
|
!strconcat(SSEVer, !strconcat("_",
|
|
!strconcat(OpcodeStr, FPSizeStr))))
|
|
RC:$src1, mem_cpat:$src2))]>;
|
|
}
|
|
|
|
/// sse12_fp_packed - SSE 1 & 2 packed instructions class
|
|
multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
|
RegisterClass RC, ValueType vt,
|
|
X86MemOperand x86memop, PatFrag mem_frag,
|
|
Domain d, bit MayLoad = 0> {
|
|
let isCommutable = 1 in
|
|
def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
|
|
OpcodeStr, [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))],d>;
|
|
let mayLoad = MayLoad in
|
|
def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
|
|
OpcodeStr, [(set RC:$dst, (OpNode RC:$src1,
|
|
(mem_frag addr:$src2)))],d>;
|
|
}
|
|
|
|
/// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
|
|
multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
|
|
string OpcodeStr, X86MemOperand x86memop,
|
|
list<dag> pat_rr, list<dag> pat_rm> {
|
|
let isCommutable = 1 in
|
|
def rr : PI<opc, MRMSrcReg, (outs RC:$dst),
|
|
(ins RC:$src1, RC:$src2), OpcodeStr, pat_rr, d>;
|
|
def rm : PI<opc, MRMSrcMem, (outs RC:$dst),
|
|
(ins RC:$src1, x86memop:$src2), OpcodeStr, pat_rm, d>;
|
|
}
|
|
|
|
/// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
|
|
multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
|
|
string asm, string SSEVer, string FPSizeStr,
|
|
X86MemOperand x86memop, PatFrag mem_frag,
|
|
Domain d> {
|
|
def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
|
|
asm, [(set RC:$dst, (
|
|
!nameconcat<Intrinsic>("int_x86_sse",
|
|
!strconcat(SSEVer, !strconcat("_",
|
|
!strconcat(OpcodeStr, FPSizeStr))))
|
|
RC:$src1, RC:$src2))], d>;
|
|
def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
|
|
asm, [(set RC:$dst, (
|
|
!nameconcat<Intrinsic>("int_x86_sse",
|
|
!strconcat(SSEVer, !strconcat("_",
|
|
!strconcat(OpcodeStr, FPSizeStr))))
|
|
RC:$src1, (mem_frag addr:$src2)))], d>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SSE1 Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Conversion Instructions
|
|
|
|
// Match intrinsics which expect XMM operand(s).
|
|
def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
|
|
"cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
|
|
def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
|
|
"cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
|
|
|
|
def CVTDQ2PSrr : PSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
|
|
def CVTDQ2PSrm : PSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
"cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
|
|
|
|
// Aliases for intrinsics
|
|
def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
|
|
"cvttss2si\t{$src, $dst|$dst, $src}",
|
|
[(set GR32:$dst,
|
|
(int_x86_sse_cvttss2si VR128:$src))]>;
|
|
def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
|
|
"cvttss2si\t{$src, $dst|$dst, $src}",
|
|
[(set GR32:$dst,
|
|
(int_x86_sse_cvttss2si(load addr:$src)))]>;
|
|
|
|
let Constraints = "$src1 = $dst" in {
|
|
def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
|
|
(outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
|
|
"cvtsi2ss\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
|
|
GR32:$src2))]>;
|
|
def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
|
|
(outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
|
|
"cvtsi2ss\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
|
|
(loadi32 addr:$src2)))]>;
|
|
}
|
|
|
|
// Compare Instructions
|
|
let Defs = [EFLAGS] in {
|
|
def COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
|
|
"comiss\t{$src2, $src1|$src1, $src2}", []>;
|
|
def COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
|
|
"comiss\t{$src2, $src1|$src1, $src2}", []>;
|
|
} // Defs = [EFLAGS]
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SSE 1 & 2 - Move Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
|
|
SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
|
|
[(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
|
|
|
|
// Loading from memory automatically zeroing upper bits.
|
|
class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
|
|
PatFrag mem_pat, string OpcodeStr> :
|
|
SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
[(set RC:$dst, (mem_pat addr:$src))]>;
|
|
|
|
// Move Instructions. Register-to-register movss/movsd is not used for FR32/64
|
|
// register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
|
|
// is used instead. Register-to-register movss/movsd is not modeled as an
|
|
// INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
|
|
// in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
|
|
let isAsmParserOnly = 1 in {
|
|
def VMOVSSrr : sse12_move_rr<FR32, v4f32,
|
|
"movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
|
|
def VMOVSDrr : sse12_move_rr<FR64, v2f64,
|
|
"movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
|
|
|
|
let canFoldAsLoad = 1, isReMaterializable = 1 in {
|
|
def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
|
|
|
|
let AddedComplexity = 20 in
|
|
def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
|
|
}
|
|
}
|
|
|
|
let Constraints = "$src1 = $dst" in {
|
|
def MOVSSrr : sse12_move_rr<FR32, v4f32,
|
|
"movss\t{$src2, $dst|$dst, $src2}">, XS;
|
|
def MOVSDrr : sse12_move_rr<FR64, v2f64,
|
|
"movsd\t{$src2, $dst|$dst, $src2}">, XD;
|
|
}
|
|
|
|
let canFoldAsLoad = 1, isReMaterializable = 1 in {
|
|
def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
|
|
|
|
let AddedComplexity = 20 in
|
|
def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
|
|
}
|
|
|
|
let AddedComplexity = 15 in {
|
|
// Extract the low 32-bit value from one vector and insert it into another.
|
|
def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
|
|
(MOVSSrr (v4f32 VR128:$src1),
|
|
(EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
|
|
// Extract the low 64-bit value from one vector and insert it into another.
|
|
def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
|
|
(MOVSDrr (v2f64 VR128:$src1),
|
|
(EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
|
|
}
|
|
|
|
// Implicitly promote a 32-bit scalar to a vector.
|
|
def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
|
|
(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
|
|
// Implicitly promote a 64-bit scalar to a vector.
|
|
def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
|
|
(INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
|
|
|
|
let AddedComplexity = 20 in {
|
|
// MOVSSrm zeros the high parts of the register; represent this
|
|
// with SUBREG_TO_REG.
|
|
def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
|
|
(SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
|
|
def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
|
|
(SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
|
|
def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
|
|
(SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
|
|
// MOVSDrm zeros the high parts of the register; represent this
|
|
// with SUBREG_TO_REG.
|
|
def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
|
|
(SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
|
|
def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
|
|
(SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
|
|
def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
|
|
(SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
|
|
def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
|
|
(SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
|
|
def : Pat<(v2f64 (X86vzload addr:$src)),
|
|
(SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
|
|
}
|
|
|
|
// Store scalar value to memory.
|
|
def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
|
|
"movss\t{$src, $dst|$dst, $src}",
|
|
[(store FR32:$src, addr:$dst)]>;
|
|
def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
|
|
"movsd\t{$src, $dst|$dst, $src}",
|
|
[(store FR64:$src, addr:$dst)]>;
|
|
|
|
let isAsmParserOnly = 1 in {
|
|
def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
|
|
"movss\t{$src, $dst|$dst, $src}",
|
|
[(store FR32:$src, addr:$dst)]>, XS, VEX_4V;
|
|
def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
|
|
"movsd\t{$src, $dst|$dst, $src}",
|
|
[(store FR64:$src, addr:$dst)]>, XD, VEX_4V;
|
|
}
|
|
|
|
// Extract and store.
|
|
def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
|
|
addr:$dst),
|
|
(MOVSSmr addr:$dst,
|
|
(EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
|
|
def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
|
|
addr:$dst),
|
|
(MOVSDmr addr:$dst,
|
|
(EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SSE 1 & 2 - Conversion Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Conversion instructions
|
|
def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
|
|
"cvttss2si\t{$src, $dst|$dst, $src}",
|
|
[(set GR32:$dst, (fp_to_sint FR32:$src))]>;
|
|
def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
|
|
"cvttss2si\t{$src, $dst|$dst, $src}",
|
|
[(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
|
|
def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
|
|
"cvttsd2si\t{$src, $dst|$dst, $src}",
|
|
[(set GR32:$dst, (fp_to_sint FR64:$src))]>;
|
|
def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
|
|
"cvttsd2si\t{$src, $dst|$dst, $src}",
|
|
[(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
|
|
|
|
def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
|
|
"cvtsi2ss\t{$src, $dst|$dst, $src}",
|
|
[(set FR32:$dst, (sint_to_fp GR32:$src))]>;
|
|
def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
|
|
"cvtsi2ss\t{$src, $dst|$dst, $src}",
|
|
[(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
|
|
def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
|
|
"cvtsi2sd\t{$src, $dst|$dst, $src}",
|
|
[(set FR64:$dst, (sint_to_fp GR32:$src))]>;
|
|
def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
|
|
"cvtsi2sd\t{$src, $dst|$dst, $src}",
|
|
[(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
|
|
|
|
// Match intrinsics which expect XMM operand(s).
|
|
def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
|
|
"cvtss2si\t{$src, $dst|$dst, $src}",
|
|
[(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
|
|
def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
|
|
"cvtss2si\t{$src, $dst|$dst, $src}",
|
|
[(set GR32:$dst, (int_x86_sse_cvtss2si
|
|
(load addr:$src)))]>;
|
|
def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
|
|
"cvtsd2si\t{$src, $dst|$dst, $src}",
|
|
[(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
|
|
def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
|
|
"cvtsd2si\t{$src, $dst|$dst, $src}",
|
|
[(set GR32:$dst, (int_x86_sse2_cvtsd2si
|
|
(load addr:$src)))]>;
|
|
|
|
// Match intrinsics which expect MM and XMM operand(s).
|
|
def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
|
|
"cvtps2pi\t{$src, $dst|$dst, $src}",
|
|
[(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
|
|
def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
|
|
"cvtps2pi\t{$src, $dst|$dst, $src}",
|
|
[(set VR64:$dst, (int_x86_sse_cvtps2pi
|
|
(load addr:$src)))]>;
|
|
def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
|
|
"cvtpd2pi\t{$src, $dst|$dst, $src}",
|
|
[(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
|
|
def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
|
|
"cvtpd2pi\t{$src, $dst|$dst, $src}",
|
|
[(set VR64:$dst, (int_x86_sse_cvtpd2pi
|
|
(memop addr:$src)))]>;
|
|
|
|
// Match intrinsics which expect MM and XMM operand(s).
|
|
def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
|
|
"cvttps2pi\t{$src, $dst|$dst, $src}",
|
|
[(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
|
|
def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
|
|
"cvttps2pi\t{$src, $dst|$dst, $src}",
|
|
[(set VR64:$dst, (int_x86_sse_cvttps2pi
|
|
(load addr:$src)))]>;
|
|
def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
|
|
"cvttpd2pi\t{$src, $dst|$dst, $src}",
|
|
[(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
|
|
def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
|
|
"cvttpd2pi\t{$src, $dst|$dst, $src}",
|
|
[(set VR64:$dst, (int_x86_sse_cvttpd2pi
|
|
(memop addr:$src)))]>;
|
|
|
|
let Constraints = "$src1 = $dst" in {
|
|
def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
|
|
(outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
|
|
"cvtpi2ps\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
|
|
VR64:$src2))]>;
|
|
def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
|
|
(outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
|
|
"cvtpi2ps\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
|
|
(load addr:$src2)))]>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SSE 1 & 2 - Compare Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
multiclass sse12_cmp<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int,
|
|
string asm, Domain d, Operand sse_imm_op> {
|
|
def rri : PIi8<0xC2, MRMSrcReg,
|
|
(outs RC:$dst), (ins RC:$src1, RC:$src, sse_imm_op:$cc), asm,
|
|
[(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
|
|
def rmi : PIi8<0xC2, MRMSrcMem,
|
|
(outs RC:$dst), (ins RC:$src1, f128mem:$src, sse_imm_op:$cc), asm,
|
|
[(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
|
|
}
|
|
|
|
// FIXME: rename instructions to only use the class above
|
|
multiclass sse12_cmp_alt<RegisterClass RC, string asm, Domain d,
|
|
Operand sse_imm_op> {
|
|
def rri_alt : PIi8<0xC2, MRMSrcReg,
|
|
(outs RC:$dst), (ins RC:$src1, RC:$src, sse_imm_op:$src2), asm,
|
|
[], d>;
|
|
def rmi_alt : PIi8<0xC2, MRMSrcMem,
|
|
(outs RC:$dst), (ins RC:$src1, f128mem:$src, sse_imm_op:$src2), asm,
|
|
[], d>;
|
|
}
|
|
|
|
multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
|
|
Operand sse_imm_op, string asm> {
|
|
def rr : SIi8<0xC2, MRMSrcReg,
|
|
(outs RC:$dst), (ins RC:$src1, RC:$src, sse_imm_op:$cc),
|
|
asm, []>;
|
|
let mayLoad = 1 in
|
|
def rm : SIi8<0xC2, MRMSrcMem,
|
|
(outs RC:$dst), (ins RC:$src1, x86memop:$src, sse_imm_op:$cc),
|
|
asm, []>;
|
|
}
|
|
|
|
// FIXME: rename instructions to only use the class above
|
|
multiclass sse12_cmp_scalar_alt<RegisterClass RC, X86MemOperand x86memop,
|
|
Operand sse_imm_op, string asm> {
|
|
def rr_alt : SIi8<0xC2, MRMSrcReg,
|
|
(outs RC:$dst), (ins RC:$src1, RC:$src, sse_imm_op:$src2),
|
|
asm, []>;
|
|
let mayLoad = 1 in
|
|
def rm_alt : SIi8<0xC2, MRMSrcMem,
|
|
(outs RC:$dst), (ins RC:$src1, x86memop:$src, sse_imm_op:$src2),
|
|
asm, []>;
|
|
}
|
|
|
|
let neverHasSideEffects = 1, isAsmParserOnly = 1 in {
|
|
defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC,
|
|
"cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
|
|
XS, VEX_4V;
|
|
defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC,
|
|
"cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
|
|
XD, VEX_4V;
|
|
|
|
// Accept explicit immediate argument form instead of comparison code.
|
|
let isAsmParserOnly = 1 in {
|
|
defm VCMPSS : sse12_cmp_scalar_alt<FR32, f32mem, i8imm,
|
|
"cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
|
|
XS, VEX_4V;
|
|
defm VCMPSD : sse12_cmp_scalar_alt<FR64, f32mem, i8imm,
|
|
"cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
|
|
XD, VEX_4V;
|
|
}
|
|
}
|
|
|
|
let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
|
|
defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC,
|
|
"cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
|
|
defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC,
|
|
"cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
|
|
|
|
// Accept explicit immediate argument form instead of comparison code.
|
|
let isAsmParserOnly = 1 in {
|
|
defm CMPSS : sse12_cmp_scalar_alt<FR32, f32mem, i8imm,
|
|
"cmpss\t{$src2, $src, $dst|$dst, $src, $src2}">, XS;
|
|
defm CMPSD : sse12_cmp_scalar_alt<FR64, f32mem, i8imm,
|
|
"cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}">, XD;
|
|
}
|
|
}
|
|
|
|
let Defs = [EFLAGS] in {
|
|
def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
|
|
"ucomiss\t{$src2, $src1|$src1, $src2}",
|
|
[(set EFLAGS, (X86cmp FR32:$src1, FR32:$src2))]>;
|
|
def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
|
|
"ucomiss\t{$src2, $src1|$src1, $src2}",
|
|
[(set EFLAGS, (X86cmp FR32:$src1, (loadf32 addr:$src2)))]>;
|
|
def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
|
|
"ucomisd\t{$src2, $src1|$src1, $src2}",
|
|
[(set EFLAGS, (X86cmp FR64:$src1, FR64:$src2))]>;
|
|
def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
|
|
"ucomisd\t{$src2, $src1|$src1, $src2}",
|
|
[(set EFLAGS, (X86cmp FR64:$src1, (loadf64 addr:$src2)))]>;
|
|
} // Defs = [EFLAGS]
|
|
|
|
// Aliases to match intrinsics which expect XMM operand(s).
|
|
let Constraints = "$src1 = $dst" in {
|
|
def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
|
|
(outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src, SSECC:$cc),
|
|
"cmp${cc}ss\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse_cmp_ss
|
|
VR128:$src1,
|
|
VR128:$src, imm:$cc))]>;
|
|
def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
|
|
(outs VR128:$dst),
|
|
(ins VR128:$src1, f32mem:$src, SSECC:$cc),
|
|
"cmp${cc}ss\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
|
|
(load addr:$src), imm:$cc))]>;
|
|
|
|
def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
|
|
(outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src, SSECC:$cc),
|
|
"cmp${cc}sd\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
|
|
VR128:$src, imm:$cc))]>;
|
|
def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
|
|
(outs VR128:$dst),
|
|
(ins VR128:$src1, f64mem:$src, SSECC:$cc),
|
|
"cmp${cc}sd\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
|
|
(load addr:$src), imm:$cc))]>;
|
|
}
|
|
|
|
let Defs = [EFLAGS] in {
|
|
def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
|
|
"ucomiss\t{$src2, $src1|$src1, $src2}",
|
|
[(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
|
|
VR128:$src2))]>;
|
|
def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
|
|
"ucomiss\t{$src2, $src1|$src1, $src2}",
|
|
[(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
|
|
(load addr:$src2)))]>;
|
|
def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
|
|
"ucomisd\t{$src2, $src1|$src1, $src2}",
|
|
[(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
|
|
VR128:$src2))]>;
|
|
def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
|
|
"ucomisd\t{$src2, $src1|$src1, $src2}",
|
|
[(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
|
|
(load addr:$src2)))]>;
|
|
|
|
def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
|
|
"comiss\t{$src2, $src1|$src1, $src2}",
|
|
[(set EFLAGS, (X86comi (v4f32 VR128:$src1),
|
|
VR128:$src2))]>;
|
|
def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
|
|
"comiss\t{$src2, $src1|$src1, $src2}",
|
|
[(set EFLAGS, (X86comi (v4f32 VR128:$src1),
|
|
(load addr:$src2)))]>;
|
|
def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
|
|
"comisd\t{$src2, $src1|$src1, $src2}",
|
|
[(set EFLAGS, (X86comi (v2f64 VR128:$src1),
|
|
VR128:$src2))]>;
|
|
def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
|
|
"comisd\t{$src2, $src1|$src1, $src2}",
|
|
[(set EFLAGS, (X86comi (v2f64 VR128:$src1),
|
|
(load addr:$src2)))]>;
|
|
} // Defs = [EFLAGS]
|
|
|
|
let Constraints = "$src1 = $dst" in {
|
|
defm CMPPS : sse12_cmp<VR128, f128mem, int_x86_sse_cmp_ps,
|
|
"cmp${cc}ps\t{$src, $dst|$dst, $src}", SSEPackedSingle, SSECC>,
|
|
TB;
|
|
defm CMPPD : sse12_cmp<VR128, f128mem, int_x86_sse2_cmp_pd,
|
|
"cmp${cc}pd\t{$src, $dst|$dst, $src}", SSEPackedDouble, SSECC>,
|
|
TB, OpSize;
|
|
}
|
|
let isAsmParserOnly = 1 in {
|
|
defm VCMPPS : sse12_cmp<VR128, f128mem, int_x86_sse_cmp_ps,
|
|
"cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
|
|
SSEPackedSingle, SSECC>, VEX_4V;
|
|
defm VCMPPD : sse12_cmp<VR128, f128mem, int_x86_sse2_cmp_pd,
|
|
"cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
|
|
SSEPackedSingle, SSECC>, OpSize, VEX_4V;
|
|
}
|
|
|
|
let isAsmParserOnly = 1, Pattern = []<dag> in {
|
|
// Accept explicit immediate argument form instead of comparison code.
|
|
let Constraints = "$src1 = $dst" in {
|
|
defm CMPPS : sse12_cmp_alt<VR128,
|
|
"cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
|
|
SSEPackedSingle, i8imm>, TB;
|
|
defm CMPPD : sse12_cmp_alt<VR128,
|
|
"cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
|
|
SSEPackedDouble, i8imm>, TB, OpSize;
|
|
}
|
|
defm VCMPPS : sse12_cmp_alt<VR128,
|
|
"cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src}",
|
|
SSEPackedSingle, i8imm>, VEX_4V;
|
|
defm VCMPPD : sse12_cmp_alt<VR128,
|
|
"cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
|
|
SSEPackedSingle, i8imm>, OpSize, VEX_4V;
|
|
}
|
|
|
|
def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
|
|
(CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
|
|
def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
|
|
(CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
|
|
def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
|
|
(CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
|
|
def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
|
|
(CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SSE 1 & 2 - Shuffle Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// sse12_shuffle - sse 1 & 2 shuffle instructions
|
|
multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
|
|
ValueType vt, string asm, PatFrag mem_frag,
|
|
Domain d, bit IsConvertibleToThreeAddress = 0> {
|
|
def rmi : PIi8<0xC6, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, f128mem:$src2, i8imm:$src3), asm,
|
|
[(set VR128:$dst, (vt (shufp:$src3
|
|
VR128:$src1, (mem_frag addr:$src2))))], d>;
|
|
let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
|
|
def rri : PIi8<0xC6, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2, i8imm:$src3), asm,
|
|
[(set VR128:$dst,
|
|
(vt (shufp:$src3 VR128:$src1, VR128:$src2)))], d>;
|
|
}
|
|
|
|
let isAsmParserOnly = 1 in {
|
|
defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
|
|
"shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
|
|
memopv4f32, SSEPackedSingle>, VEX_4V;
|
|
defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
|
|
"shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
|
|
memopv2f64, SSEPackedDouble>, OpSize, VEX_4V;
|
|
}
|
|
|
|
let Constraints = "$src1 = $dst" in {
|
|
defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
|
|
"shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|
memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
|
|
TB;
|
|
defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
|
|
"shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|
memopv2f64, SSEPackedDouble>, TB, OpSize;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SSE 1 & 2 - Unpack Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
|
|
multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
|
|
PatFrag mem_frag, RegisterClass RC,
|
|
X86MemOperand x86memop, string asm,
|
|
Domain d> {
|
|
def rr : PI<opc, MRMSrcReg,
|
|
(outs RC:$dst), (ins RC:$src1, RC:$src2),
|
|
asm, [(set RC:$dst,
|
|
(vt (OpNode RC:$src1, RC:$src2)))], d>;
|
|
def rm : PI<opc, MRMSrcMem,
|
|
(outs RC:$dst), (ins RC:$src1, x86memop:$src2),
|
|
asm, [(set RC:$dst,
|
|
(vt (OpNode RC:$src1,
|
|
(mem_frag addr:$src2))))], d>;
|
|
}
|
|
|
|
let AddedComplexity = 10 in {
|
|
let isAsmParserOnly = 1 in {
|
|
defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
|
|
VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|
SSEPackedSingle>, VEX_4V;
|
|
defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
|
|
VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|
SSEPackedDouble>, OpSize, VEX_4V;
|
|
defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
|
|
VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|
SSEPackedSingle>, VEX_4V;
|
|
defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
|
|
VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|
SSEPackedDouble>, OpSize, VEX_4V;
|
|
}
|
|
|
|
let Constraints = "$src1 = $dst" in {
|
|
defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
|
|
VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
|
|
SSEPackedSingle>, TB;
|
|
defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
|
|
VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
|
|
SSEPackedDouble>, TB, OpSize;
|
|
defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
|
|
VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
|
|
SSEPackedSingle>, TB;
|
|
defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
|
|
VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
|
|
SSEPackedDouble>, TB, OpSize;
|
|
} // Constraints = "$src1 = $dst"
|
|
} // AddedComplexity
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SSE 1 & 2 - Extract Floating-Point Sign mask
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
|
|
multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
|
|
Domain d> {
|
|
def rr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
|
|
!strconcat(asm, "\t{$src, $dst|$dst, $src}"),
|
|
[(set GR32:$dst, (Int RC:$src))], d>;
|
|
}
|
|
|
|
// Mask creation
|
|
defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
|
|
SSEPackedSingle>, TB;
|
|
defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
|
|
SSEPackedDouble>, TB, OpSize;
|
|
|
|
let isAsmParserOnly = 1 in {
|
|
defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
|
|
"movmskps", SSEPackedSingle>, VEX;
|
|
defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
|
|
"movmskpd", SSEPackedDouble>, OpSize,
|
|
VEX;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
|
|
// names that start with 'Fs'.
|
|
|
|
// Alias instructions that map fld0 to pxor for sse.
|
|
let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
|
|
canFoldAsLoad = 1 in {
|
|
// FIXME: Set encoding to pseudo!
|
|
def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
|
|
[(set FR32:$dst, fp32imm0)]>,
|
|
Requires<[HasSSE1]>, TB, OpSize;
|
|
def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
|
|
[(set FR64:$dst, fpimm0)]>,
|
|
Requires<[HasSSE2]>, TB, OpSize;
|
|
}
|
|
|
|
// Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
|
|
// bits are disregarded.
|
|
let neverHasSideEffects = 1 in {
|
|
def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
|
|
"movaps\t{$src, $dst|$dst, $src}", []>;
|
|
def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
|
|
"movapd\t{$src, $dst|$dst, $src}", []>;
|
|
}
|
|
|
|
// Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
|
|
// bits are disregarded.
|
|
let canFoldAsLoad = 1, isReMaterializable = 1 in {
|
|
def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
|
|
"movaps\t{$src, $dst|$dst, $src}",
|
|
[(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
|
|
def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
|
|
"movapd\t{$src, $dst|$dst, $src}",
|
|
[(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SSE 1 & 2 - Logical Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
|
|
///
|
|
multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
|
|
SDNode OpNode, bit MayLoad = 0> {
|
|
let isAsmParserOnly = 1 in {
|
|
defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
|
|
"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode, FR32,
|
|
f32, f128mem, memopfsf32, SSEPackedSingle, MayLoad>, VEX_4V;
|
|
|
|
defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
|
|
"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode, FR64,
|
|
f64, f128mem, memopfsf64, SSEPackedDouble, MayLoad>, OpSize,
|
|
VEX_4V;
|
|
}
|
|
|
|
let Constraints = "$src1 = $dst" in {
|
|
defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
|
|
"ps\t{$src2, $dst|$dst, $src2}"), OpNode, FR32, f32,
|
|
f128mem, memopfsf32, SSEPackedSingle, MayLoad>, TB;
|
|
|
|
defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
|
|
"pd\t{$src2, $dst|$dst, $src2}"), OpNode, FR64, f64,
|
|
f128mem, memopfsf64, SSEPackedDouble, MayLoad>, TB, OpSize;
|
|
}
|
|
}
|
|
|
|
// Alias bitwise logical operations using SSE logical ops on packed FP values.
|
|
defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
|
|
defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
|
|
defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
|
|
|
|
let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
|
|
defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef, 1>;
|
|
|
|
/// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
|
|
///
|
|
multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
|
|
SDNode OpNode, int HasPat = 0,
|
|
list<list<dag>> Pattern = []> {
|
|
let isAsmParserOnly = 1 in {
|
|
defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
|
|
!strconcat(OpcodeStr, "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
f128mem,
|
|
!if(HasPat, Pattern[0], // rr
|
|
[(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
|
|
VR128:$src2)))]),
|
|
!if(HasPat, Pattern[2], // rm
|
|
[(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
|
|
(memopv2i64 addr:$src2)))])>,
|
|
VEX_4V;
|
|
|
|
defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
|
|
!strconcat(OpcodeStr, "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
f128mem,
|
|
!if(HasPat, Pattern[1], // rr
|
|
[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
|
|
(bc_v2i64 (v2f64
|
|
VR128:$src2))))]),
|
|
!if(HasPat, Pattern[3], // rm
|
|
[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
|
|
(memopv2i64 addr:$src2)))])>,
|
|
OpSize, VEX_4V;
|
|
}
|
|
let Constraints = "$src1 = $dst" in {
|
|
defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
|
|
!strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"), f128mem,
|
|
!if(HasPat, Pattern[0], // rr
|
|
[(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
|
|
VR128:$src2)))]),
|
|
!if(HasPat, Pattern[2], // rm
|
|
[(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
|
|
(memopv2i64 addr:$src2)))])>, TB;
|
|
|
|
defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
|
|
!strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"), f128mem,
|
|
!if(HasPat, Pattern[1], // rr
|
|
[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
|
|
(bc_v2i64 (v2f64
|
|
VR128:$src2))))]),
|
|
!if(HasPat, Pattern[3], // rm
|
|
[(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
|
|
(memopv2i64 addr:$src2)))])>,
|
|
TB, OpSize;
|
|
}
|
|
}
|
|
|
|
defm AND : sse12_fp_packed_logical<0x54, "and", and>;
|
|
defm OR : sse12_fp_packed_logical<0x56, "or", or>;
|
|
defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
|
|
let isCommutable = 0 in
|
|
defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
|
|
// single r+r
|
|
[(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
|
|
(bc_v2i64 (v4i32 immAllOnesV))),
|
|
VR128:$src2)))],
|
|
// double r+r
|
|
[(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
|
|
(bc_v2i64 (v2f64 VR128:$src2))))],
|
|
// single r+m
|
|
[(set VR128:$dst, (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
|
|
(bc_v2i64 (v4i32 immAllOnesV))),
|
|
(memopv2i64 addr:$src2))))],
|
|
// double r+m
|
|
[(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
|
|
(memopv2i64 addr:$src2)))]]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SSE 1 & 2 - Arithmetic Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// basic_sse12_fp_binop_rm - SSE 1 & 2 binops come in both scalar and
|
|
/// vector forms.
|
|
///
|
|
/// In addition, we also have a special variant of the scalar form here to
|
|
/// represent the associated intrinsic operation. This form is unlike the
|
|
/// plain scalar form, in that it takes an entire vector (instead of a scalar)
|
|
/// and leaves the top elements unmodified (therefore these cannot be commuted).
|
|
///
|
|
/// These three forms can each be reg+reg or reg+mem.
|
|
///
|
|
multiclass basic_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
|
|
SDNode OpNode> {
|
|
|
|
let isAsmParserOnly = 1 in {
|
|
defm V#NAME#SS : sse12_fp_scalar<opc,
|
|
!strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
OpNode, FR32, f32mem>, XS, VEX_4V;
|
|
|
|
defm V#NAME#SD : sse12_fp_scalar<opc,
|
|
!strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
OpNode, FR64, f64mem>, XD, VEX_4V;
|
|
|
|
defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
|
|
"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
|
|
VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle>,
|
|
VEX_4V;
|
|
|
|
defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
|
|
"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
|
|
VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble>,
|
|
OpSize, VEX_4V;
|
|
|
|
defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
|
|
!strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
"", "_ss", ssmem, sse_load_f32>, XS, VEX_4V;
|
|
|
|
defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
|
|
!strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
"2", "_sd", sdmem, sse_load_f64>, XD, VEX_4V;
|
|
}
|
|
|
|
let Constraints = "$src1 = $dst" in {
|
|
defm SS : sse12_fp_scalar<opc,
|
|
!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
|
|
OpNode, FR32, f32mem>, XS;
|
|
|
|
defm SD : sse12_fp_scalar<opc,
|
|
!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
|
|
OpNode, FR64, f64mem>, XD;
|
|
|
|
defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
|
|
"ps\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v4f32,
|
|
f128mem, memopv4f32, SSEPackedSingle>, TB;
|
|
|
|
defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
|
|
"pd\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v2f64,
|
|
f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
|
|
|
|
defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
|
|
!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
|
|
"", "_ss", ssmem, sse_load_f32>, XS;
|
|
|
|
defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
|
|
!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
|
|
"2", "_sd", sdmem, sse_load_f64>, XD;
|
|
}
|
|
}
|
|
|
|
// Arithmetic instructions
|
|
defm ADD : basic_sse12_fp_binop_rm<0x58, "add", fadd>;
|
|
defm MUL : basic_sse12_fp_binop_rm<0x59, "mul", fmul>;
|
|
|
|
let isCommutable = 0 in {
|
|
defm SUB : basic_sse12_fp_binop_rm<0x5C, "sub", fsub>;
|
|
defm DIV : basic_sse12_fp_binop_rm<0x5E, "div", fdiv>;
|
|
}
|
|
|
|
/// sse12_fp_binop_rm - Other SSE 1 & 2 binops
|
|
///
|
|
/// This multiclass is like basic_sse12_fp_binop_rm, with the addition of
|
|
/// instructions for a full-vector intrinsic form. Operations that map
|
|
/// onto C operators don't use this form since they just use the plain
|
|
/// vector form instead of having a separate vector intrinsic form.
|
|
///
|
|
multiclass sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
|
|
SDNode OpNode> {
|
|
|
|
let isAsmParserOnly = 1 in {
|
|
// Scalar operation, reg+reg.
|
|
defm V#NAME#SS : sse12_fp_scalar<opc,
|
|
!strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
OpNode, FR32, f32mem>, XS, VEX_4V;
|
|
|
|
defm V#NAME#SD : sse12_fp_scalar<opc,
|
|
!strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
OpNode, FR64, f64mem>, XD, VEX_4V;
|
|
|
|
defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
|
|
"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
|
|
VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle>,
|
|
VEX_4V;
|
|
|
|
defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
|
|
"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
|
|
VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble>,
|
|
OpSize, VEX_4V;
|
|
|
|
defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
|
|
!strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
"", "_ss", ssmem, sse_load_f32>, XS, VEX_4V;
|
|
|
|
defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
|
|
!strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
"2", "_sd", sdmem, sse_load_f64>, XD, VEX_4V;
|
|
|
|
defm V#NAME#PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
|
|
!strconcat(OpcodeStr, "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
"", "_ps", f128mem, memopv4f32, SSEPackedSingle>, VEX_4V;
|
|
|
|
defm V#NAME#PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
|
|
!strconcat(OpcodeStr, "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
"2", "_pd", f128mem, memopv2f64, SSEPackedDouble>, OpSize,
|
|
VEX_4V;
|
|
}
|
|
|
|
let Constraints = "$src1 = $dst" in {
|
|
// Scalar operation, reg+reg.
|
|
defm SS : sse12_fp_scalar<opc,
|
|
!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
|
|
OpNode, FR32, f32mem>, XS;
|
|
defm SD : sse12_fp_scalar<opc,
|
|
!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
|
|
OpNode, FR64, f64mem>, XD;
|
|
defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
|
|
"ps\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v4f32,
|
|
f128mem, memopv4f32, SSEPackedSingle>, TB;
|
|
|
|
defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
|
|
"pd\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v2f64,
|
|
f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
|
|
|
|
defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
|
|
!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
|
|
"", "_ss", ssmem, sse_load_f32>, XS;
|
|
|
|
defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
|
|
!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
|
|
"2", "_sd", sdmem, sse_load_f64>, XD;
|
|
|
|
defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
|
|
!strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
|
|
"", "_ps", f128mem, memopv4f32, SSEPackedSingle>, TB;
|
|
|
|
defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
|
|
!strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
|
|
"2", "_pd", f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
|
|
}
|
|
}
|
|
|
|
let isCommutable = 0 in {
|
|
defm MAX : sse12_fp_binop_rm<0x5F, "max", X86fmax>;
|
|
defm MIN : sse12_fp_binop_rm<0x5D, "min", X86fmin>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SSE packed FP Instructions
|
|
|
|
// Move Instructions
|
|
let neverHasSideEffects = 1 in
|
|
def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"movaps\t{$src, $dst|$dst, $src}", []>;
|
|
let canFoldAsLoad = 1, isReMaterializable = 1 in
|
|
def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
"movaps\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
|
|
|
|
def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
|
|
"movaps\t{$src, $dst|$dst, $src}",
|
|
[(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
|
|
|
|
let neverHasSideEffects = 1 in
|
|
def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"movups\t{$src, $dst|$dst, $src}", []>;
|
|
let canFoldAsLoad = 1, isReMaterializable = 1 in
|
|
def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
"movups\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (loadv4f32 addr:$src))]>;
|
|
def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
|
|
"movups\t{$src, $dst|$dst, $src}",
|
|
[(store (v4f32 VR128:$src), addr:$dst)]>;
|
|
|
|
// Intrinsic forms of MOVUPS load and store
|
|
let canFoldAsLoad = 1, isReMaterializable = 1 in
|
|
def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
"movups\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
|
|
def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
|
|
"movups\t{$src, $dst|$dst, $src}",
|
|
[(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
|
|
|
|
let Constraints = "$src1 = $dst" in {
|
|
let AddedComplexity = 20 in {
|
|
def MOVLPSrm : PSI<0x12, MRMSrcMem,
|
|
(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
|
|
"movlps\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst,
|
|
(movlp VR128:$src1,
|
|
(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
|
|
def MOVHPSrm : PSI<0x16, MRMSrcMem,
|
|
(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
|
|
"movhps\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst,
|
|
(movlhps VR128:$src1,
|
|
(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
|
|
} // AddedComplexity
|
|
} // Constraints = "$src1 = $dst"
|
|
|
|
|
|
def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
|
|
(MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
|
|
|
|
def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
|
|
"movlps\t{$src, $dst|$dst, $src}",
|
|
[(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
|
|
(iPTR 0))), addr:$dst)]>;
|
|
|
|
// v2f64 extract element 1 is always custom lowered to unpack high to low
|
|
// and extract element 0 so the non-store version isn't too horrible.
|
|
def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
|
|
"movhps\t{$src, $dst|$dst, $src}",
|
|
[(store (f64 (vector_extract
|
|
(unpckh (bc_v2f64 (v4f32 VR128:$src)),
|
|
(undef)), (iPTR 0))), addr:$dst)]>;
|
|
|
|
let Constraints = "$src1 = $dst" in {
|
|
let AddedComplexity = 20 in {
|
|
def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2),
|
|
"movlhps\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst,
|
|
(v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
|
|
|
|
def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2),
|
|
"movhlps\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst,
|
|
(v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
|
|
} // AddedComplexity
|
|
} // Constraints = "$src1 = $dst"
|
|
|
|
let AddedComplexity = 20 in {
|
|
def : Pat<(v4f32 (movddup VR128:$src, (undef))),
|
|
(MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
|
|
def : Pat<(v2i64 (movddup VR128:$src, (undef))),
|
|
(MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
|
|
}
|
|
|
|
|
|
|
|
// Arithmetic
|
|
|
|
/// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
|
|
///
|
|
/// In addition, we also have a special variant of the scalar form here to
|
|
/// represent the associated intrinsic operation. This form is unlike the
|
|
/// plain scalar form, in that it takes an entire vector (instead of a
|
|
/// scalar) and leaves the top elements undefined.
|
|
///
|
|
/// And, we have a special variant form for a full-vector intrinsic form.
|
|
///
|
|
/// These four forms can each have a reg or a mem operand, so there are a
|
|
/// total of eight "instructions".
|
|
///
|
|
multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
|
|
SDNode OpNode,
|
|
Intrinsic F32Int,
|
|
Intrinsic V4F32Int,
|
|
bit Commutable = 0> {
|
|
// Scalar operation, reg.
|
|
def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
|
|
!strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
|
|
[(set FR32:$dst, (OpNode FR32:$src))]> {
|
|
let isCommutable = Commutable;
|
|
}
|
|
|
|
// Scalar operation, mem.
|
|
def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
|
|
!strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
|
|
[(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
|
|
Requires<[HasSSE1, OptForSize]>;
|
|
|
|
// Vector operation, reg.
|
|
def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
|
|
let isCommutable = Commutable;
|
|
}
|
|
|
|
// Vector operation, mem.
|
|
def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
|
|
|
|
// Intrinsic operation, reg.
|
|
def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
!strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst, (F32Int VR128:$src))]> {
|
|
let isCommutable = Commutable;
|
|
}
|
|
|
|
// Intrinsic operation, mem.
|
|
def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
|
|
!strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
|
|
|
|
// Vector intrinsic operation, reg
|
|
def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst, (V4F32Int VR128:$src))]> {
|
|
let isCommutable = Commutable;
|
|
}
|
|
|
|
// Vector intrinsic operation, mem
|
|
def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
!strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
|
|
}
|
|
|
|
// Square root.
|
|
defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
|
|
int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
|
|
|
|
// Reciprocal approximations. Note that these typically require refinement
|
|
// in order to obtain suitable precision.
|
|
defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
|
|
int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
|
|
defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
|
|
int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
|
|
|
|
// Prefetch intrinsic.
|
|
def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
|
|
"prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
|
|
def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
|
|
"prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
|
|
def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
|
|
"prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
|
|
def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
|
|
"prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
|
|
|
|
// Non-temporal stores
|
|
def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
|
|
"movntps\t{$src, $dst|$dst, $src}",
|
|
[(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
|
|
|
|
let AddedComplexity = 400 in { // Prefer non-temporal versions
|
|
def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
|
|
"movntps\t{$src, $dst|$dst, $src}",
|
|
[(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
|
|
|
|
def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
|
|
"movntdq\t{$src, $dst|$dst, $src}",
|
|
[(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
|
|
|
|
def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
|
|
"movnti\t{$src, $dst|$dst, $src}",
|
|
[(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
|
|
TB, Requires<[HasSSE2]>;
|
|
|
|
def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
|
|
"movnti\t{$src, $dst|$dst, $src}",
|
|
[(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
|
|
TB, Requires<[HasSSE2]>;
|
|
}
|
|
|
|
// Load, store, and memory fence
|
|
def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
|
|
TB, Requires<[HasSSE1]>;
|
|
|
|
// MXCSR register
|
|
def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
|
|
"ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
|
|
def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
|
|
"stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
|
|
|
|
// Alias instructions that map zero vector to pxor / xorp* for sse.
|
|
// We set canFoldAsLoad because this can be converted to a constant-pool
|
|
// load of an all-zeros value if folding it would be beneficial.
|
|
// FIXME: Change encoding to pseudo!
|
|
let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
|
|
isCodeGenOnly = 1 in {
|
|
def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
|
|
[(set VR128:$dst, (v4f32 immAllZerosV))]>;
|
|
def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
|
|
[(set VR128:$dst, (v2f64 immAllZerosV))]>;
|
|
let ExeDomain = SSEPackedInt in
|
|
def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
|
|
[(set VR128:$dst, (v4i32 immAllZerosV))]>;
|
|
}
|
|
|
|
def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
|
|
def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
|
|
def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
|
|
|
|
def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
|
|
(f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
// SSE2 Instructions
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
// Conversion instructions
|
|
def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
|
|
"cvtsd2ss\t{$src, $dst|$dst, $src}",
|
|
[(set FR32:$dst, (fround FR64:$src))]>;
|
|
def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
|
|
"cvtsd2ss\t{$src, $dst|$dst, $src}",
|
|
[(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
|
|
Requires<[HasSSE2, OptForSize]>;
|
|
|
|
def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"cvtps2dq\t{$src, $dst|$dst, $src}", []>;
|
|
def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
"cvtps2dq\t{$src, $dst|$dst, $src}", []>;
|
|
def COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
|
|
"comisd\t{$src2, $src1|$src1, $src2}", []>;
|
|
def COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
|
|
"comisd\t{$src2, $src1|$src1, $src2}", []>;
|
|
|
|
// SSE2 instructions with XS prefix
|
|
def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
|
|
"cvtss2sd\t{$src, $dst|$dst, $src}",
|
|
[(set FR64:$dst, (fextend FR32:$src))]>, XS,
|
|
Requires<[HasSSE2]>;
|
|
def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
|
|
"cvtss2sd\t{$src, $dst|$dst, $src}",
|
|
[(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
|
|
Requires<[HasSSE2, OptForSize]>;
|
|
|
|
def : Pat<(extloadf32 addr:$src),
|
|
(CVTSS2SDrr (MOVSSrm addr:$src))>,
|
|
Requires<[HasSSE2, OptForSpeed]>;
|
|
|
|
// Match intrinsics which expect MM and XMM operand(s).
|
|
def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
|
|
"cvtpi2pd\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
|
|
def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
|
|
"cvtpi2pd\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse_cvtpi2pd
|
|
(load addr:$src)))]>;
|
|
|
|
// Aliases for intrinsics
|
|
def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
|
|
"cvttsd2si\t{$src, $dst|$dst, $src}",
|
|
[(set GR32:$dst,
|
|
(int_x86_sse2_cvttsd2si VR128:$src))]>;
|
|
def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
|
|
"cvttsd2si\t{$src, $dst|$dst, $src}",
|
|
[(set GR32:$dst, (int_x86_sse2_cvttsd2si
|
|
(load addr:$src)))]>;
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
// SSE packed FP Instructions
|
|
|
|
// Move Instructions
|
|
let neverHasSideEffects = 1 in
|
|
def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"movapd\t{$src, $dst|$dst, $src}", []>;
|
|
let canFoldAsLoad = 1, isReMaterializable = 1 in
|
|
def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
"movapd\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
|
|
|
|
def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
|
|
"movapd\t{$src, $dst|$dst, $src}",
|
|
[(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
|
|
|
|
let neverHasSideEffects = 1 in
|
|
def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"movupd\t{$src, $dst|$dst, $src}", []>;
|
|
let canFoldAsLoad = 1 in
|
|
def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
"movupd\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (loadv2f64 addr:$src))]>;
|
|
def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
|
|
"movupd\t{$src, $dst|$dst, $src}",
|
|
[(store (v2f64 VR128:$src), addr:$dst)]>;
|
|
|
|
// Intrinsic forms of MOVUPD load and store
|
|
def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
"movupd\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
|
|
def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
|
|
"movupd\t{$src, $dst|$dst, $src}",
|
|
[(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
|
|
|
|
let Constraints = "$src1 = $dst" in {
|
|
let AddedComplexity = 20 in {
|
|
def MOVLPDrm : PDI<0x12, MRMSrcMem,
|
|
(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
|
|
"movlpd\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst,
|
|
(v2f64 (movlp VR128:$src1,
|
|
(scalar_to_vector (loadf64 addr:$src2)))))]>;
|
|
def MOVHPDrm : PDI<0x16, MRMSrcMem,
|
|
(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
|
|
"movhpd\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst,
|
|
(v2f64 (movlhps VR128:$src1,
|
|
(scalar_to_vector (loadf64 addr:$src2)))))]>;
|
|
} // AddedComplexity
|
|
} // Constraints = "$src1 = $dst"
|
|
|
|
def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
|
|
"movlpd\t{$src, $dst|$dst, $src}",
|
|
[(store (f64 (vector_extract (v2f64 VR128:$src),
|
|
(iPTR 0))), addr:$dst)]>;
|
|
|
|
// v2f64 extract element 1 is always custom lowered to unpack high to low
|
|
// and extract element 0 so the non-store version isn't too horrible.
|
|
def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
|
|
"movhpd\t{$src, $dst|$dst, $src}",
|
|
[(store (f64 (vector_extract
|
|
(v2f64 (unpckh VR128:$src, (undef))),
|
|
(iPTR 0))), addr:$dst)]>;
|
|
|
|
// SSE2 instructions without OpSize prefix
|
|
def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"cvtdq2ps\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
|
|
TB, Requires<[HasSSE2]>;
|
|
def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
|
|
"cvtdq2ps\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse2_cvtdq2ps
|
|
(bitconvert (memopv2i64 addr:$src))))]>,
|
|
TB, Requires<[HasSSE2]>;
|
|
|
|
// SSE2 instructions with XS prefix
|
|
def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"cvtdq2pd\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
|
|
XS, Requires<[HasSSE2]>;
|
|
def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
|
|
"cvtdq2pd\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse2_cvtdq2pd
|
|
(bitconvert (memopv2i64 addr:$src))))]>,
|
|
XS, Requires<[HasSSE2]>;
|
|
|
|
def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"cvtps2dq\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
|
|
def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
"cvtps2dq\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse2_cvtps2dq
|
|
(memop addr:$src)))]>;
|
|
// SSE2 packed instructions with XS prefix
|
|
def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"cvttps2dq\t{$src, $dst|$dst, $src}", []>;
|
|
def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
"cvttps2dq\t{$src, $dst|$dst, $src}", []>;
|
|
|
|
def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"cvttps2dq\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst,
|
|
(int_x86_sse2_cvttps2dq VR128:$src))]>,
|
|
XS, Requires<[HasSSE2]>;
|
|
def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
"cvttps2dq\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse2_cvttps2dq
|
|
(memop addr:$src)))]>,
|
|
XS, Requires<[HasSSE2]>;
|
|
|
|
// SSE2 packed instructions with XD prefix
|
|
def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"cvtpd2dq\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
|
|
XD, Requires<[HasSSE2]>;
|
|
def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
"cvtpd2dq\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse2_cvtpd2dq
|
|
(memop addr:$src)))]>,
|
|
XD, Requires<[HasSSE2]>;
|
|
|
|
def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"cvttpd2dq\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
|
|
def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
|
|
"cvttpd2dq\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse2_cvttpd2dq
|
|
(memop addr:$src)))]>;
|
|
|
|
// SSE2 instructions without OpSize prefix
|
|
def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
|
|
def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
|
|
"cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
|
|
|
|
def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"cvtps2pd\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
|
|
TB, Requires<[HasSSE2]>;
|
|
def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
|
|
"cvtps2pd\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse2_cvtps2pd
|
|
(load addr:$src)))]>,
|
|
TB, Requires<[HasSSE2]>;
|
|
|
|
def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
|
|
def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
"cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
|
|
|
|
|
|
def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"cvtpd2ps\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
|
|
def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
"cvtpd2ps\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse2_cvtpd2ps
|
|
(memop addr:$src)))]>;
|
|
|
|
// Match intrinsics which expect XMM operand(s).
|
|
// Aliases for intrinsics
|
|
let Constraints = "$src1 = $dst" in {
|
|
def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
|
|
(outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
|
|
"cvtsi2sd\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
|
|
GR32:$src2))]>;
|
|
def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
|
|
(outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
|
|
"cvtsi2sd\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
|
|
(loadi32 addr:$src2)))]>;
|
|
def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
|
"cvtsd2ss\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
|
|
VR128:$src2))]>;
|
|
def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
|
|
(outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
|
|
"cvtsd2ss\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
|
|
(load addr:$src2)))]>;
|
|
def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
|
"cvtss2sd\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
|
|
VR128:$src2))]>, XS,
|
|
Requires<[HasSSE2]>;
|
|
def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
|
|
(outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
|
|
"cvtss2sd\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
|
|
(load addr:$src2)))]>, XS,
|
|
Requires<[HasSSE2]>;
|
|
}
|
|
|
|
// Arithmetic
|
|
|
|
/// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
|
|
///
|
|
/// In addition, we also have a special variant of the scalar form here to
|
|
/// represent the associated intrinsic operation. This form is unlike the
|
|
/// plain scalar form, in that it takes an entire vector (instead of a
|
|
/// scalar) and leaves the top elements undefined.
|
|
///
|
|
/// And, we have a special variant form for a full-vector intrinsic form.
|
|
///
|
|
/// These four forms can each have a reg or a mem operand, so there are a
|
|
/// total of eight "instructions".
|
|
///
|
|
multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
|
|
SDNode OpNode,
|
|
Intrinsic F64Int,
|
|
Intrinsic V2F64Int,
|
|
bit Commutable = 0> {
|
|
// Scalar operation, reg.
|
|
def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
|
|
!strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
|
|
[(set FR64:$dst, (OpNode FR64:$src))]> {
|
|
let isCommutable = Commutable;
|
|
}
|
|
|
|
// Scalar operation, mem.
|
|
def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
|
|
!strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
|
|
[(set FR64:$dst, (OpNode (load addr:$src)))]>;
|
|
|
|
// Vector operation, reg.
|
|
def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
|
|
let isCommutable = Commutable;
|
|
}
|
|
|
|
// Vector operation, mem.
|
|
def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
|
|
|
|
// Intrinsic operation, reg.
|
|
def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
!strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst, (F64Int VR128:$src))]> {
|
|
let isCommutable = Commutable;
|
|
}
|
|
|
|
// Intrinsic operation, mem.
|
|
def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
|
|
!strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
|
|
|
|
// Vector intrinsic operation, reg
|
|
def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst, (V2F64Int VR128:$src))]> {
|
|
let isCommutable = Commutable;
|
|
}
|
|
|
|
// Vector intrinsic operation, mem
|
|
def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
!strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
|
|
}
|
|
|
|
// Square root.
|
|
defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
|
|
int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
|
|
|
|
// There is no f64 version of the reciprocal approximation instructions.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
// SSE integer instructions
|
|
let ExeDomain = SSEPackedInt in {
|
|
|
|
// Move Instructions
|
|
let neverHasSideEffects = 1 in
|
|
def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"movdqa\t{$src, $dst|$dst, $src}", []>;
|
|
let canFoldAsLoad = 1, mayLoad = 1 in
|
|
def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
|
|
"movdqa\t{$src, $dst|$dst, $src}",
|
|
[/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
|
|
let mayStore = 1 in
|
|
def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
|
|
"movdqa\t{$src, $dst|$dst, $src}",
|
|
[/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
|
|
let canFoldAsLoad = 1, mayLoad = 1 in
|
|
def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
|
|
"movdqu\t{$src, $dst|$dst, $src}",
|
|
[/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
|
|
XS, Requires<[HasSSE2]>;
|
|
let mayStore = 1 in
|
|
def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
|
|
"movdqu\t{$src, $dst|$dst, $src}",
|
|
[/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
|
|
XS, Requires<[HasSSE2]>;
|
|
|
|
// Intrinsic forms of MOVDQU load and store
|
|
let canFoldAsLoad = 1 in
|
|
def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
|
|
"movdqu\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
|
|
XS, Requires<[HasSSE2]>;
|
|
def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
|
|
"movdqu\t{$src, $dst|$dst, $src}",
|
|
[(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
|
|
XS, Requires<[HasSSE2]>;
|
|
|
|
let Constraints = "$src1 = $dst" in {
|
|
|
|
multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
|
|
bit Commutable = 0> {
|
|
def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
|
|
let isCommutable = Commutable;
|
|
}
|
|
def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, i128mem:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (IntId VR128:$src1,
|
|
(bitconvert (memopv2i64
|
|
addr:$src2))))]>;
|
|
}
|
|
|
|
multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
|
|
string OpcodeStr,
|
|
Intrinsic IntId, Intrinsic IntId2> {
|
|
def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
|
|
def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, i128mem:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (IntId VR128:$src1,
|
|
(bitconvert (memopv2i64 addr:$src2))))]>;
|
|
def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
|
|
(ins VR128:$src1, i32i8imm:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
|
|
}
|
|
|
|
/// PDI_binop_rm - Simple SSE2 binary operator.
|
|
multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
|
ValueType OpVT, bit Commutable = 0> {
|
|
def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
|
|
let isCommutable = Commutable;
|
|
}
|
|
def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, i128mem:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (OpVT (OpNode VR128:$src1,
|
|
(bitconvert (memopv2i64 addr:$src2)))))]>;
|
|
}
|
|
|
|
/// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
|
|
///
|
|
/// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
|
|
/// to collapse (bitconvert VT to VT) into its operand.
|
|
///
|
|
multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
|
bit Commutable = 0> {
|
|
def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
|
|
let isCommutable = Commutable;
|
|
}
|
|
def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, i128mem:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (OpNode VR128:$src1,
|
|
(memopv2i64 addr:$src2)))]>;
|
|
}
|
|
|
|
} // Constraints = "$src1 = $dst"
|
|
} // ExeDomain = SSEPackedInt
|
|
|
|
// 128-bit Integer Arithmetic
|
|
|
|
defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
|
|
defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
|
|
defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
|
|
defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
|
|
|
|
defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
|
|
defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
|
|
defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
|
|
defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
|
|
|
|
defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
|
|
defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
|
|
defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
|
|
defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
|
|
|
|
defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
|
|
defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
|
|
defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
|
|
defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
|
|
|
|
defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
|
|
|
|
defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
|
|
defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
|
|
defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
|
|
|
|
defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
|
|
|
|
defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
|
|
defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
|
|
|
|
|
|
defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
|
|
defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
|
|
defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
|
|
defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
|
|
defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
|
|
|
|
|
|
defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
|
|
int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
|
|
defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
|
|
int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
|
|
defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
|
|
int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
|
|
|
|
defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
|
|
int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
|
|
defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
|
|
int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
|
|
defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
|
|
int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
|
|
|
|
defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
|
|
int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
|
|
defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
|
|
int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
|
|
|
|
// 128-bit logical shifts.
|
|
let Constraints = "$src1 = $dst", neverHasSideEffects = 1,
|
|
ExeDomain = SSEPackedInt in {
|
|
def PSLLDQri : PDIi8<0x73, MRM7r,
|
|
(outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
|
|
"pslldq\t{$src2, $dst|$dst, $src2}", []>;
|
|
def PSRLDQri : PDIi8<0x73, MRM3r,
|
|
(outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
|
|
"psrldq\t{$src2, $dst|$dst, $src2}", []>;
|
|
// PSRADQri doesn't exist in SSE[1-3].
|
|
}
|
|
|
|
let Predicates = [HasSSE2] in {
|
|
def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
|
|
(v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
|
|
def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
|
|
(v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
|
|
def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
|
|
(v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
|
|
def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
|
|
(v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
|
|
def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
|
|
(v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
|
|
|
|
// Shift up / down and insert zero's.
|
|
def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
|
|
(v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
|
|
def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
|
|
(v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
|
|
}
|
|
|
|
// Logical
|
|
defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
|
|
defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
|
|
defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
|
|
|
|
let Constraints = "$src1 = $dst", ExeDomain = SSEPackedInt in {
|
|
def PANDNrr : PDI<0xDF, MRMSrcReg,
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
|
"pandn\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
|
|
VR128:$src2)))]>;
|
|
|
|
def PANDNrm : PDI<0xDF, MRMSrcMem,
|
|
(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
|
"pandn\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
|
|
(memopv2i64 addr:$src2))))]>;
|
|
}
|
|
|
|
// SSE2 Integer comparison
|
|
defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
|
|
defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
|
|
defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
|
|
defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
|
|
defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
|
|
defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
|
|
|
|
def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
|
|
(PCMPEQBrr VR128:$src1, VR128:$src2)>;
|
|
def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
|
|
(PCMPEQBrm VR128:$src1, addr:$src2)>;
|
|
def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
|
|
(PCMPEQWrr VR128:$src1, VR128:$src2)>;
|
|
def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
|
|
(PCMPEQWrm VR128:$src1, addr:$src2)>;
|
|
def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
|
|
(PCMPEQDrr VR128:$src1, VR128:$src2)>;
|
|
def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
|
|
(PCMPEQDrm VR128:$src1, addr:$src2)>;
|
|
|
|
def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
|
|
(PCMPGTBrr VR128:$src1, VR128:$src2)>;
|
|
def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
|
|
(PCMPGTBrm VR128:$src1, addr:$src2)>;
|
|
def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
|
|
(PCMPGTWrr VR128:$src1, VR128:$src2)>;
|
|
def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
|
|
(PCMPGTWrm VR128:$src1, addr:$src2)>;
|
|
def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
|
|
(PCMPGTDrr VR128:$src1, VR128:$src2)>;
|
|
def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
|
|
(PCMPGTDrm VR128:$src1, addr:$src2)>;
|
|
|
|
|
|
// Pack instructions
|
|
defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
|
|
defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
|
|
defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
|
|
|
|
let ExeDomain = SSEPackedInt in {
|
|
|
|
// Shuffle and unpack instructions
|
|
let AddedComplexity = 5 in {
|
|
def PSHUFDri : PDIi8<0x70, MRMSrcReg,
|
|
(outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
|
|
"pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|
[(set VR128:$dst, (v4i32 (pshufd:$src2
|
|
VR128:$src1, (undef))))]>;
|
|
def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
|
|
(outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
|
|
"pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|
[(set VR128:$dst, (v4i32 (pshufd:$src2
|
|
(bc_v4i32 (memopv2i64 addr:$src1)),
|
|
(undef))))]>;
|
|
}
|
|
|
|
// SSE2 with ImmT == Imm8 and XS prefix.
|
|
def PSHUFHWri : Ii8<0x70, MRMSrcReg,
|
|
(outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
|
|
"pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|
[(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
|
|
(undef))))]>,
|
|
XS, Requires<[HasSSE2]>;
|
|
def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
|
|
(outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
|
|
"pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|
[(set VR128:$dst, (v8i16 (pshufhw:$src2
|
|
(bc_v8i16 (memopv2i64 addr:$src1)),
|
|
(undef))))]>,
|
|
XS, Requires<[HasSSE2]>;
|
|
|
|
// SSE2 with ImmT == Imm8 and XD prefix.
|
|
def PSHUFLWri : Ii8<0x70, MRMSrcReg,
|
|
(outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
|
|
"pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|
[(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
|
|
(undef))))]>,
|
|
XD, Requires<[HasSSE2]>;
|
|
def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
|
|
(outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
|
|
"pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|
[(set VR128:$dst, (v8i16 (pshuflw:$src2
|
|
(bc_v8i16 (memopv2i64 addr:$src1)),
|
|
(undef))))]>,
|
|
XD, Requires<[HasSSE2]>;
|
|
|
|
// Unpack instructions
|
|
multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
|
|
PatFrag unp_frag, PatFrag bc_frag> {
|
|
def rr : PDI<opc, MRMSrcReg,
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
|
!strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
|
|
def rm : PDI<opc, MRMSrcMem,
|
|
(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
|
!strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (unp_frag VR128:$src1,
|
|
(bc_frag (memopv2i64
|
|
addr:$src2))))]>;
|
|
}
|
|
|
|
let Constraints = "$src1 = $dst" in {
|
|
defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>;
|
|
defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>;
|
|
defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>;
|
|
|
|
/// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
|
|
/// knew to collapse (bitconvert VT to VT) into its operand.
|
|
def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
|
"punpcklqdq\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst,
|
|
(v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
|
|
def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
|
|
(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
|
"punpcklqdq\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst,
|
|
(v2i64 (unpckl VR128:$src1,
|
|
(memopv2i64 addr:$src2))))]>;
|
|
|
|
defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>;
|
|
defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>;
|
|
defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>;
|
|
|
|
/// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
|
|
/// knew to collapse (bitconvert VT to VT) into its operand.
|
|
def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
|
"punpckhqdq\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst,
|
|
(v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
|
|
def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
|
|
(outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
|
|
"punpckhqdq\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst,
|
|
(v2i64 (unpckh VR128:$src1,
|
|
(memopv2i64 addr:$src2))))]>;
|
|
}
|
|
|
|
// Extract / Insert
|
|
def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
|
|
(outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
|
|
"pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
|
|
[(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
|
|
imm:$src2))]>;
|
|
let Constraints = "$src1 = $dst" in {
|
|
def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
|
|
(outs VR128:$dst), (ins VR128:$src1,
|
|
GR32:$src2, i32i8imm:$src3),
|
|
"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|
[(set VR128:$dst,
|
|
(X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
|
|
def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
|
|
(outs VR128:$dst), (ins VR128:$src1,
|
|
i16mem:$src2, i32i8imm:$src3),
|
|
"pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|
[(set VR128:$dst,
|
|
(X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
|
|
imm:$src3))]>;
|
|
}
|
|
|
|
// Mask creation
|
|
def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
|
|
"pmovmskb\t{$src, $dst|$dst, $src}",
|
|
[(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
|
|
|
|
// Conditional store
|
|
let Uses = [EDI] in
|
|
def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
|
|
"maskmovdqu\t{$mask, $src|$src, $mask}",
|
|
[(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
|
|
|
|
let Uses = [RDI] in
|
|
def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
|
|
"maskmovdqu\t{$mask, $src|$src, $mask}",
|
|
[(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
|
|
|
|
} // ExeDomain = SSEPackedInt
|
|
|
|
// Non-temporal stores
|
|
def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
|
|
"movntpd\t{$src, $dst|$dst, $src}",
|
|
[(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
|
|
let ExeDomain = SSEPackedInt in
|
|
def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
|
|
"movntdq\t{$src, $dst|$dst, $src}",
|
|
[(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
|
|
def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
|
|
"movnti\t{$src, $dst|$dst, $src}",
|
|
[(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
|
|
TB, Requires<[HasSSE2]>;
|
|
|
|
let AddedComplexity = 400 in { // Prefer non-temporal versions
|
|
def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
|
|
"movntpd\t{$src, $dst|$dst, $src}",
|
|
[(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
|
|
|
|
let ExeDomain = SSEPackedInt in
|
|
def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
|
|
"movntdq\t{$src, $dst|$dst, $src}",
|
|
[(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
|
|
}
|
|
|
|
// Flush cache
|
|
def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
|
|
"clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
|
|
TB, Requires<[HasSSE2]>;
|
|
|
|
// Load, store, and memory fence
|
|
def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
|
|
"lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
|
|
def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
|
|
"mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
|
|
|
|
// Pause. This "instruction" is encoded as "rep; nop", so even though it
|
|
// was introduced with SSE2, it's backward compatible.
|
|
def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
|
|
|
|
//TODO: custom lower this so as to never even generate the noop
|
|
def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
|
|
(i8 0)), (NOOP)>;
|
|
def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
|
|
def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
|
|
def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
|
|
(i8 1)), (MFENCE)>;
|
|
|
|
// Alias instructions that map zero vector to pxor / xorp* for sse.
|
|
// We set canFoldAsLoad because this can be converted to a constant-pool
|
|
// load of an all-ones value if folding it would be beneficial.
|
|
let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
|
|
isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
|
|
// FIXME: Change encoding to pseudo.
|
|
def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
|
|
[(set VR128:$dst, (v4i32 immAllOnesV))]>;
|
|
|
|
def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
|
|
"movd\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst,
|
|
(v4i32 (scalar_to_vector GR32:$src)))]>;
|
|
def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
|
|
"movd\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst,
|
|
(v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
|
|
|
|
def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
|
|
"movd\t{$src, $dst|$dst, $src}",
|
|
[(set FR32:$dst, (bitconvert GR32:$src))]>;
|
|
|
|
def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
|
|
"movd\t{$src, $dst|$dst, $src}",
|
|
[(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
|
|
|
|
// SSE2 instructions with XS prefix
|
|
def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
|
|
"movq\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst,
|
|
(v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
|
|
Requires<[HasSSE2]>;
|
|
def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
|
|
"movq\t{$src, $dst|$dst, $src}",
|
|
[(store (i64 (vector_extract (v2i64 VR128:$src),
|
|
(iPTR 0))), addr:$dst)]>;
|
|
|
|
def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
|
|
(f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
|
|
|
|
def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
|
|
"movd\t{$src, $dst|$dst, $src}",
|
|
[(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
|
|
(iPTR 0)))]>;
|
|
def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
|
|
"movd\t{$src, $dst|$dst, $src}",
|
|
[(store (i32 (vector_extract (v4i32 VR128:$src),
|
|
(iPTR 0))), addr:$dst)]>;
|
|
|
|
def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
|
|
"movd\t{$src, $dst|$dst, $src}",
|
|
[(set GR32:$dst, (bitconvert FR32:$src))]>;
|
|
def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
|
|
"movd\t{$src, $dst|$dst, $src}",
|
|
[(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
|
|
|
|
// Store / copy lower 64-bits of a XMM register.
|
|
def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
|
|
"movq\t{$src, $dst|$dst, $src}",
|
|
[(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
|
|
|
|
// movd / movq to XMM register zero-extends
|
|
let AddedComplexity = 15 in {
|
|
def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
|
|
"movd\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (v4i32 (X86vzmovl
|
|
(v4i32 (scalar_to_vector GR32:$src)))))]>;
|
|
// This is X86-64 only.
|
|
def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
|
|
"mov{d|q}\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (v2i64 (X86vzmovl
|
|
(v2i64 (scalar_to_vector GR64:$src)))))]>;
|
|
}
|
|
|
|
let AddedComplexity = 20 in {
|
|
def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
|
|
"movd\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst,
|
|
(v4i32 (X86vzmovl (v4i32 (scalar_to_vector
|
|
(loadi32 addr:$src))))))]>;
|
|
|
|
def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
|
|
(MOVZDI2PDIrm addr:$src)>;
|
|
def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
|
|
(MOVZDI2PDIrm addr:$src)>;
|
|
def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
|
|
(MOVZDI2PDIrm addr:$src)>;
|
|
|
|
def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
|
|
"movq\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst,
|
|
(v2i64 (X86vzmovl (v2i64 (scalar_to_vector
|
|
(loadi64 addr:$src))))))]>, XS,
|
|
Requires<[HasSSE2]>;
|
|
|
|
def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
|
|
(MOVZQI2PQIrm addr:$src)>;
|
|
def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
|
|
(MOVZQI2PQIrm addr:$src)>;
|
|
def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
|
|
}
|
|
|
|
// Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
|
|
// IA32 document. movq xmm1, xmm2 does clear the high bits.
|
|
let AddedComplexity = 15 in
|
|
def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"movq\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
|
|
XS, Requires<[HasSSE2]>;
|
|
|
|
let AddedComplexity = 20 in {
|
|
def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
|
|
"movq\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (v2i64 (X86vzmovl
|
|
(loadv2i64 addr:$src))))]>,
|
|
XS, Requires<[HasSSE2]>;
|
|
|
|
def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
|
|
(MOVZPQILo2PQIrm addr:$src)>;
|
|
}
|
|
|
|
// Instructions for the disassembler
|
|
// xr = XMM register
|
|
// xm = mem64
|
|
|
|
def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"movq\t{$src, $dst|$dst, $src}", []>, XS;
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
// SSE3 Instructions
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
// Conversion Instructions
|
|
def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
"cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
|
|
def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
|
|
def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
"cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
|
|
def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
|
|
|
|
// Move Instructions
|
|
def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"movshdup\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (v4f32 (movshdup
|
|
VR128:$src, (undef))))]>;
|
|
def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
"movshdup\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (movshdup
|
|
(memopv4f32 addr:$src), (undef)))]>;
|
|
|
|
def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"movsldup\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (v4f32 (movsldup
|
|
VR128:$src, (undef))))]>;
|
|
def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
|
|
"movsldup\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (movsldup
|
|
(memopv4f32 addr:$src), (undef)))]>;
|
|
|
|
def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
"movddup\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
|
|
def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
|
|
"movddup\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst,
|
|
(v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
|
|
(undef))))]>;
|
|
|
|
def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
|
|
(undef)),
|
|
(MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
|
|
|
|
let AddedComplexity = 5 in {
|
|
def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
|
|
(MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
|
|
def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
|
|
(MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
|
|
def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
|
|
(MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
|
|
def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
|
|
(MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
|
|
}
|
|
|
|
// Arithmetic
|
|
let Constraints = "$src1 = $dst" in {
|
|
def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
|
"addsubps\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
|
|
VR128:$src2))]>;
|
|
def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
|
|
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
|
"addsubps\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
|
|
(memop addr:$src2)))]>;
|
|
def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
|
|
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
|
"addsubpd\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
|
|
VR128:$src2))]>;
|
|
def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
|
|
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
|
"addsubpd\t{$src2, $dst|$dst, $src2}",
|
|
[(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
|
|
(memop addr:$src2)))]>;
|
|
}
|
|
|
|
def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
|
|
"lddqu\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
|
|
|
|
// Horizontal ops
|
|
class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
|
|
: S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
|
|
class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
|
|
: S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
|
|
class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
|
|
: S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
|
|
class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
|
|
: S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
|
|
|
|
let Constraints = "$src1 = $dst" in {
|
|
def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
|
|
def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
|
|
def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
|
|
def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
|
|
def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
|
|
def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
|
|
def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
|
|
def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
|
|
}
|
|
|
|
// Thread synchronization
|
|
def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
|
|
[(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
|
|
def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
|
|
[(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
|
|
|
|
// vector_shuffle v1, <undef> <1, 1, 3, 3>
|
|
let AddedComplexity = 15 in
|
|
def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
|
|
(MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
|
|
let AddedComplexity = 20 in
|
|
def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
|
|
(MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
|
|
|
|
// vector_shuffle v1, <undef> <0, 0, 2, 2>
|
|
let AddedComplexity = 15 in
|
|
def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
|
|
(MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
|
|
let AddedComplexity = 20 in
|
|
def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
|
|
(MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
// SSSE3 Instructions
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
/// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
|
|
multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
|
|
Intrinsic IntId64, Intrinsic IntId128> {
|
|
def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
[(set VR64:$dst, (IntId64 VR64:$src))]>;
|
|
|
|
def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
[(set VR64:$dst,
|
|
(IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
|
|
|
|
def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src),
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst, (IntId128 VR128:$src))]>,
|
|
OpSize;
|
|
|
|
def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins i128mem:$src),
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst,
|
|
(IntId128
|
|
(bitconvert (memopv16i8 addr:$src))))]>, OpSize;
|
|
}
|
|
|
|
/// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
|
|
multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
|
|
Intrinsic IntId64, Intrinsic IntId128> {
|
|
def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
|
|
(ins VR64:$src),
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
[(set VR64:$dst, (IntId64 VR64:$src))]>;
|
|
|
|
def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
|
|
(ins i64mem:$src),
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
[(set VR64:$dst,
|
|
(IntId64
|
|
(bitconvert (memopv4i16 addr:$src))))]>;
|
|
|
|
def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src),
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst, (IntId128 VR128:$src))]>,
|
|
OpSize;
|
|
|
|
def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins i128mem:$src),
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst,
|
|
(IntId128
|
|
(bitconvert (memopv8i16 addr:$src))))]>, OpSize;
|
|
}
|
|
|
|
/// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
|
|
multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
|
|
Intrinsic IntId64, Intrinsic IntId128> {
|
|
def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
|
|
(ins VR64:$src),
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
[(set VR64:$dst, (IntId64 VR64:$src))]>;
|
|
|
|
def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
|
|
(ins i64mem:$src),
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
[(set VR64:$dst,
|
|
(IntId64
|
|
(bitconvert (memopv2i32 addr:$src))))]>;
|
|
|
|
def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src),
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst, (IntId128 VR128:$src))]>,
|
|
OpSize;
|
|
|
|
def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins i128mem:$src),
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst,
|
|
(IntId128
|
|
(bitconvert (memopv4i32 addr:$src))))]>, OpSize;
|
|
}
|
|
|
|
defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
|
|
int_x86_ssse3_pabs_b,
|
|
int_x86_ssse3_pabs_b_128>;
|
|
defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
|
|
int_x86_ssse3_pabs_w,
|
|
int_x86_ssse3_pabs_w_128>;
|
|
defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
|
|
int_x86_ssse3_pabs_d,
|
|
int_x86_ssse3_pabs_d_128>;
|
|
|
|
/// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
|
|
let Constraints = "$src1 = $dst" in {
|
|
multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
|
|
Intrinsic IntId64, Intrinsic IntId128,
|
|
bit Commutable = 0> {
|
|
def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
|
|
(ins VR64:$src1, VR64:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
|
|
let isCommutable = Commutable;
|
|
}
|
|
def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
|
|
(ins VR64:$src1, i64mem:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR64:$dst,
|
|
(IntId64 VR64:$src1,
|
|
(bitconvert (memopv8i8 addr:$src2))))]>;
|
|
|
|
def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
|
|
OpSize {
|
|
let isCommutable = Commutable;
|
|
}
|
|
def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, i128mem:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst,
|
|
(IntId128 VR128:$src1,
|
|
(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
|
|
}
|
|
}
|
|
|
|
/// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
|
|
let Constraints = "$src1 = $dst" in {
|
|
multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
|
|
Intrinsic IntId64, Intrinsic IntId128,
|
|
bit Commutable = 0> {
|
|
def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
|
|
(ins VR64:$src1, VR64:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
|
|
let isCommutable = Commutable;
|
|
}
|
|
def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
|
|
(ins VR64:$src1, i64mem:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR64:$dst,
|
|
(IntId64 VR64:$src1,
|
|
(bitconvert (memopv4i16 addr:$src2))))]>;
|
|
|
|
def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
|
|
OpSize {
|
|
let isCommutable = Commutable;
|
|
}
|
|
def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, i128mem:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst,
|
|
(IntId128 VR128:$src1,
|
|
(bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
|
|
}
|
|
}
|
|
|
|
/// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
|
|
let Constraints = "$src1 = $dst" in {
|
|
multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
|
|
Intrinsic IntId64, Intrinsic IntId128,
|
|
bit Commutable = 0> {
|
|
def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
|
|
(ins VR64:$src1, VR64:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
|
|
let isCommutable = Commutable;
|
|
}
|
|
def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
|
|
(ins VR64:$src1, i64mem:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR64:$dst,
|
|
(IntId64 VR64:$src1,
|
|
(bitconvert (memopv2i32 addr:$src2))))]>;
|
|
|
|
def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
|
|
OpSize {
|
|
let isCommutable = Commutable;
|
|
}
|
|
def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, i128mem:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst,
|
|
(IntId128 VR128:$src1,
|
|
(bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
|
|
}
|
|
}
|
|
|
|
let ImmT = NoImm in { // None of these have i8 immediate fields.
|
|
defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
|
|
int_x86_ssse3_phadd_w,
|
|
int_x86_ssse3_phadd_w_128>;
|
|
defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
|
|
int_x86_ssse3_phadd_d,
|
|
int_x86_ssse3_phadd_d_128>;
|
|
defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
|
|
int_x86_ssse3_phadd_sw,
|
|
int_x86_ssse3_phadd_sw_128>;
|
|
defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
|
|
int_x86_ssse3_phsub_w,
|
|
int_x86_ssse3_phsub_w_128>;
|
|
defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
|
|
int_x86_ssse3_phsub_d,
|
|
int_x86_ssse3_phsub_d_128>;
|
|
defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
|
|
int_x86_ssse3_phsub_sw,
|
|
int_x86_ssse3_phsub_sw_128>;
|
|
defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
|
|
int_x86_ssse3_pmadd_ub_sw,
|
|
int_x86_ssse3_pmadd_ub_sw_128>;
|
|
defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
|
|
int_x86_ssse3_pmul_hr_sw,
|
|
int_x86_ssse3_pmul_hr_sw_128, 1>;
|
|
|
|
defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
|
|
int_x86_ssse3_pshuf_b,
|
|
int_x86_ssse3_pshuf_b_128>;
|
|
defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
|
|
int_x86_ssse3_psign_b,
|
|
int_x86_ssse3_psign_b_128>;
|
|
defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
|
|
int_x86_ssse3_psign_w,
|
|
int_x86_ssse3_psign_w_128>;
|
|
defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
|
|
int_x86_ssse3_psign_d,
|
|
int_x86_ssse3_psign_d_128>;
|
|
}
|
|
|
|
// palignr patterns.
|
|
let Constraints = "$src1 = $dst" in {
|
|
def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
|
|
(ins VR64:$src1, VR64:$src2, i8imm:$src3),
|
|
"palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|
[]>;
|
|
def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
|
|
(ins VR64:$src1, i64mem:$src2, i8imm:$src3),
|
|
"palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|
[]>;
|
|
|
|
def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2, i8imm:$src3),
|
|
"palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|
[]>, OpSize;
|
|
def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, i128mem:$src2, i8imm:$src3),
|
|
"palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
|
[]>, OpSize;
|
|
}
|
|
|
|
let AddedComplexity = 5 in {
|
|
|
|
def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
|
|
(PALIGNR64rr VR64:$src2, VR64:$src1,
|
|
(SHUFFLE_get_palign_imm VR64:$src3))>,
|
|
Requires<[HasSSSE3]>;
|
|
def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
|
|
(PALIGNR64rr VR64:$src2, VR64:$src1,
|
|
(SHUFFLE_get_palign_imm VR64:$src3))>,
|
|
Requires<[HasSSSE3]>;
|
|
def : Pat<(v2f32 (palign:$src3 VR64:$src1, VR64:$src2)),
|
|
(PALIGNR64rr VR64:$src2, VR64:$src1,
|
|
(SHUFFLE_get_palign_imm VR64:$src3))>,
|
|
Requires<[HasSSSE3]>;
|
|
def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
|
|
(PALIGNR64rr VR64:$src2, VR64:$src1,
|
|
(SHUFFLE_get_palign_imm VR64:$src3))>,
|
|
Requires<[HasSSSE3]>;
|
|
def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
|
|
(PALIGNR64rr VR64:$src2, VR64:$src1,
|
|
(SHUFFLE_get_palign_imm VR64:$src3))>,
|
|
Requires<[HasSSSE3]>;
|
|
|
|
def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
|
|
(PALIGNR128rr VR128:$src2, VR128:$src1,
|
|
(SHUFFLE_get_palign_imm VR128:$src3))>,
|
|
Requires<[HasSSSE3]>;
|
|
def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
|
|
(PALIGNR128rr VR128:$src2, VR128:$src1,
|
|
(SHUFFLE_get_palign_imm VR128:$src3))>,
|
|
Requires<[HasSSSE3]>;
|
|
def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
|
|
(PALIGNR128rr VR128:$src2, VR128:$src1,
|
|
(SHUFFLE_get_palign_imm VR128:$src3))>,
|
|
Requires<[HasSSSE3]>;
|
|
def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
|
|
(PALIGNR128rr VR128:$src2, VR128:$src1,
|
|
(SHUFFLE_get_palign_imm VR128:$src3))>,
|
|
Requires<[HasSSSE3]>;
|
|
}
|
|
|
|
def : Pat<(X86pshufb VR128:$src, VR128:$mask),
|
|
(PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
|
|
def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
|
|
(PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
// Non-Instruction Patterns
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
// extload f32 -> f64. This matches load+fextend because we have a hack in
|
|
// the isel (PreprocessForFPConvert) that can introduce loads after dag
|
|
// combine.
|
|
// Since these loads aren't folded into the fextend, we have to match it
|
|
// explicitly here.
|
|
let Predicates = [HasSSE2] in
|
|
def : Pat<(fextend (loadf32 addr:$src)),
|
|
(CVTSS2SDrm addr:$src)>;
|
|
|
|
// bit_convert
|
|
let Predicates = [HasSSE2] in {
|
|
def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
|
|
def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
|
|
def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
|
|
def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
|
|
def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
|
|
def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
|
|
def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
|
|
def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
|
|
def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
|
|
def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
|
|
def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
|
|
def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
|
|
def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
|
|
def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
|
|
def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
|
|
def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
|
|
def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
|
|
def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
|
|
def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
|
|
def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
|
|
def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
|
|
def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
|
|
def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
|
|
def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
|
|
def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
|
|
def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
|
|
def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
|
|
def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
|
|
def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
|
|
def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
|
|
}
|
|
|
|
// Move scalar to XMM zero-extended
|
|
// movd to XMM register zero-extends
|
|
let AddedComplexity = 15 in {
|
|
// Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
|
|
def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
|
|
(MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
|
|
def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
|
|
(MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
|
|
def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
|
|
(MOVSSrr (v4f32 (V_SET0PS)),
|
|
(f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
|
|
def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
|
|
(MOVSSrr (v4i32 (V_SET0PI)),
|
|
(EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
|
|
}
|
|
|
|
// Splat v2f64 / v2i64
|
|
let AddedComplexity = 10 in {
|
|
def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
|
|
(UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
|
def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
|
|
(UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
|
def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
|
|
(PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
|
def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
|
|
(PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
|
|
}
|
|
|
|
// Special unary SHUFPSrri case.
|
|
def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
|
|
(SHUFPSrri VR128:$src1, VR128:$src1,
|
|
(SHUFFLE_get_shuf_imm VR128:$src3))>;
|
|
let AddedComplexity = 5 in
|
|
def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
|
|
(PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
|
|
Requires<[HasSSE2]>;
|
|
// Special unary SHUFPDrri case.
|
|
def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
|
|
(SHUFPDrri VR128:$src1, VR128:$src1,
|
|
(SHUFFLE_get_shuf_imm VR128:$src3))>,
|
|
Requires<[HasSSE2]>;
|
|
// Special unary SHUFPDrri case.
|
|
def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
|
|
(SHUFPDrri VR128:$src1, VR128:$src1,
|
|
(SHUFFLE_get_shuf_imm VR128:$src3))>,
|
|
Requires<[HasSSE2]>;
|
|
// Unary v4f32 shuffle with PSHUF* in order to fold a load.
|
|
def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
|
|
(PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
|
|
Requires<[HasSSE2]>;
|
|
|
|
// Special binary v4i32 shuffle cases with SHUFPS.
|
|
def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
|
|
(SHUFPSrri VR128:$src1, VR128:$src2,
|
|
(SHUFFLE_get_shuf_imm VR128:$src3))>,
|
|
Requires<[HasSSE2]>;
|
|
def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
|
|
(SHUFPSrmi VR128:$src1, addr:$src2,
|
|
(SHUFFLE_get_shuf_imm VR128:$src3))>,
|
|
Requires<[HasSSE2]>;
|
|
// Special binary v2i64 shuffle cases using SHUFPDrri.
|
|
def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
|
|
(SHUFPDrri VR128:$src1, VR128:$src2,
|
|
(SHUFFLE_get_shuf_imm VR128:$src3))>,
|
|
Requires<[HasSSE2]>;
|
|
|
|
// vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
|
|
let AddedComplexity = 15 in {
|
|
def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
|
|
(PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
|
|
Requires<[OptForSpeed, HasSSE2]>;
|
|
def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
|
|
(PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
|
|
Requires<[OptForSpeed, HasSSE2]>;
|
|
}
|
|
let AddedComplexity = 10 in {
|
|
def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
|
|
(UNPCKLPSrr VR128:$src, VR128:$src)>;
|
|
def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
|
|
(PUNPCKLBWrr VR128:$src, VR128:$src)>;
|
|
def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
|
|
(PUNPCKLWDrr VR128:$src, VR128:$src)>;
|
|
def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
|
|
(PUNPCKLDQrr VR128:$src, VR128:$src)>;
|
|
}
|
|
|
|
// vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
|
|
let AddedComplexity = 15 in {
|
|
def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
|
|
(PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
|
|
Requires<[OptForSpeed, HasSSE2]>;
|
|
def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
|
|
(PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
|
|
Requires<[OptForSpeed, HasSSE2]>;
|
|
}
|
|
let AddedComplexity = 10 in {
|
|
def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
|
|
(UNPCKHPSrr VR128:$src, VR128:$src)>;
|
|
def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
|
|
(PUNPCKHBWrr VR128:$src, VR128:$src)>;
|
|
def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
|
|
(PUNPCKHWDrr VR128:$src, VR128:$src)>;
|
|
def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
|
|
(PUNPCKHDQrr VR128:$src, VR128:$src)>;
|
|
}
|
|
|
|
let AddedComplexity = 20 in {
|
|
// vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
|
|
def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
|
|
(MOVLHPSrr VR128:$src1, VR128:$src2)>;
|
|
|
|
// vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
|
|
def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
|
|
(MOVHLPSrr VR128:$src1, VR128:$src2)>;
|
|
|
|
// vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
|
|
def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
|
|
(MOVHLPSrr VR128:$src1, VR128:$src1)>;
|
|
def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
|
|
(MOVHLPSrr VR128:$src1, VR128:$src1)>;
|
|
}
|
|
|
|
let AddedComplexity = 20 in {
|
|
// vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
|
|
def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
|
|
(MOVLPSrm VR128:$src1, addr:$src2)>;
|
|
def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
|
|
(MOVLPDrm VR128:$src1, addr:$src2)>;
|
|
def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
|
|
(MOVLPSrm VR128:$src1, addr:$src2)>;
|
|
def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
|
|
(MOVLPDrm VR128:$src1, addr:$src2)>;
|
|
}
|
|
|
|
// (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
|
|
def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
|
|
(MOVLPSmr addr:$src1, VR128:$src2)>;
|
|
def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
|
|
(MOVLPDmr addr:$src1, VR128:$src2)>;
|
|
def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
|
|
addr:$src1),
|
|
(MOVLPSmr addr:$src1, VR128:$src2)>;
|
|
def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
|
|
(MOVLPDmr addr:$src1, VR128:$src2)>;
|
|
|
|
let AddedComplexity = 15 in {
|
|
// Setting the lowest element in the vector.
|
|
def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
|
|
(MOVSSrr (v4i32 VR128:$src1),
|
|
(EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
|
|
def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
|
|
(MOVSDrr (v2i64 VR128:$src1),
|
|
(EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
|
|
|
|
// vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
|
|
def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
|
|
(MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
|
|
Requires<[HasSSE2]>;
|
|
def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
|
|
(MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
|
|
Requires<[HasSSE2]>;
|
|
}
|
|
|
|
// vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
|
|
// fall back to this for SSE1)
|
|
def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
|
|
(SHUFPSrri VR128:$src2, VR128:$src1,
|
|
(SHUFFLE_get_shuf_imm VR128:$src3))>;
|
|
|
|
// Set lowest element and zero upper elements.
|
|
def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
|
|
(MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
|
|
|
|
// Some special case pandn patterns.
|
|
def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
|
|
VR128:$src2)),
|
|
(PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
|
def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
|
|
VR128:$src2)),
|
|
(PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
|
def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
|
|
VR128:$src2)),
|
|
(PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
|
|
|
|
def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
|
|
(memop addr:$src2))),
|
|
(PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
|
def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
|
|
(memop addr:$src2))),
|
|
(PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
|
def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
|
|
(memop addr:$src2))),
|
|
(PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
|
|
|
|
// vector -> vector casts
|
|
def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
|
|
(Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
|
|
def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
|
|
(Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
|
|
def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
|
|
(Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
|
|
def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
|
|
(Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
|
|
|
|
// Use movaps / movups for SSE integer load / store (one byte shorter).
|
|
def : Pat<(alignedloadv4i32 addr:$src),
|
|
(MOVAPSrm addr:$src)>;
|
|
def : Pat<(loadv4i32 addr:$src),
|
|
(MOVUPSrm addr:$src)>;
|
|
def : Pat<(alignedloadv2i64 addr:$src),
|
|
(MOVAPSrm addr:$src)>;
|
|
def : Pat<(loadv2i64 addr:$src),
|
|
(MOVUPSrm addr:$src)>;
|
|
|
|
def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
|
|
(MOVAPSmr addr:$dst, VR128:$src)>;
|
|
def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
|
|
(MOVAPSmr addr:$dst, VR128:$src)>;
|
|
def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
|
|
(MOVAPSmr addr:$dst, VR128:$src)>;
|
|
def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
|
|
(MOVAPSmr addr:$dst, VR128:$src)>;
|
|
def : Pat<(store (v2i64 VR128:$src), addr:$dst),
|
|
(MOVUPSmr addr:$dst, VR128:$src)>;
|
|
def : Pat<(store (v4i32 VR128:$src), addr:$dst),
|
|
(MOVUPSmr addr:$dst, VR128:$src)>;
|
|
def : Pat<(store (v8i16 VR128:$src), addr:$dst),
|
|
(MOVUPSmr addr:$dst, VR128:$src)>;
|
|
def : Pat<(store (v16i8 VR128:$src), addr:$dst),
|
|
(MOVUPSmr addr:$dst, VR128:$src)>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SSE4.1 Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
|
|
string OpcodeStr,
|
|
Intrinsic V4F32Int,
|
|
Intrinsic V2F64Int> {
|
|
// Intrinsic operation, reg.
|
|
// Vector intrinsic operation, reg
|
|
def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
|
|
(outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
|
|
!strconcat(OpcodeStr,
|
|
"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
[(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
|
|
OpSize;
|
|
|
|
// Vector intrinsic operation, mem
|
|
def PSm_Int : Ii8<opcps, MRMSrcMem,
|
|
(outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
|
|
!strconcat(OpcodeStr,
|
|
"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
[(set VR128:$dst,
|
|
(V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
|
|
TA, OpSize,
|
|
Requires<[HasSSE41]>;
|
|
|
|
// Vector intrinsic operation, reg
|
|
def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
|
|
(outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
|
|
!strconcat(OpcodeStr,
|
|
"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
[(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
|
|
OpSize;
|
|
|
|
// Vector intrinsic operation, mem
|
|
def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
|
|
(outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
|
|
!strconcat(OpcodeStr,
|
|
"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
[(set VR128:$dst,
|
|
(V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
|
|
OpSize;
|
|
}
|
|
|
|
let Constraints = "$src1 = $dst" in {
|
|
multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
|
|
string OpcodeStr,
|
|
Intrinsic F32Int,
|
|
Intrinsic F64Int> {
|
|
// Intrinsic operation, reg.
|
|
def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
|
|
(outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
|
[(set VR128:$dst,
|
|
(F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
|
|
OpSize;
|
|
|
|
// Intrinsic operation, mem.
|
|
def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
|
|
(outs VR128:$dst),
|
|
(ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
|
[(set VR128:$dst,
|
|
(F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
|
|
OpSize;
|
|
|
|
// Intrinsic operation, reg.
|
|
def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
|
|
(outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
|
[(set VR128:$dst,
|
|
(F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
|
|
OpSize;
|
|
|
|
// Intrinsic operation, mem.
|
|
def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
|
|
(outs VR128:$dst),
|
|
(ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
|
[(set VR128:$dst,
|
|
(F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
|
|
OpSize;
|
|
}
|
|
}
|
|
|
|
// FP round - roundss, roundps, roundsd, roundpd
|
|
defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
|
|
int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
|
|
defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
|
|
int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
|
|
|
|
// SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
|
|
multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
|
|
Intrinsic IntId128> {
|
|
def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src),
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
|
|
def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins i128mem:$src),
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst,
|
|
(IntId128
|
|
(bitconvert (memopv8i16 addr:$src))))]>, OpSize;
|
|
}
|
|
|
|
defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
|
|
int_x86_sse41_phminposuw>;
|
|
|
|
/// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
|
|
let Constraints = "$src1 = $dst" in {
|
|
multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
|
|
Intrinsic IntId128, bit Commutable = 0> {
|
|
def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
|
|
OpSize {
|
|
let isCommutable = Commutable;
|
|
}
|
|
def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, i128mem:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst,
|
|
(IntId128 VR128:$src1,
|
|
(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
|
|
}
|
|
}
|
|
|
|
defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
|
|
int_x86_sse41_pcmpeqq, 1>;
|
|
defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
|
|
int_x86_sse41_packusdw, 0>;
|
|
defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
|
|
int_x86_sse41_pminsb, 1>;
|
|
defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
|
|
int_x86_sse41_pminsd, 1>;
|
|
defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
|
|
int_x86_sse41_pminud, 1>;
|
|
defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
|
|
int_x86_sse41_pminuw, 1>;
|
|
defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
|
|
int_x86_sse41_pmaxsb, 1>;
|
|
defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
|
|
int_x86_sse41_pmaxsd, 1>;
|
|
defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
|
|
int_x86_sse41_pmaxud, 1>;
|
|
defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
|
|
int_x86_sse41_pmaxuw, 1>;
|
|
|
|
defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
|
|
|
|
def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
|
|
(PCMPEQQrr VR128:$src1, VR128:$src2)>;
|
|
def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
|
|
(PCMPEQQrm VR128:$src1, addr:$src2)>;
|
|
|
|
/// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
|
|
let Constraints = "$src1 = $dst" in {
|
|
multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
|
|
SDNode OpNode, Intrinsic IntId128,
|
|
bit Commutable = 0> {
|
|
def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (OpNode (OpVT VR128:$src1),
|
|
VR128:$src2))]>, OpSize {
|
|
let isCommutable = Commutable;
|
|
}
|
|
def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
|
|
OpSize {
|
|
let isCommutable = Commutable;
|
|
}
|
|
def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, i128mem:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst,
|
|
(OpVT (OpNode VR128:$src1, (memop addr:$src2))))]>, OpSize;
|
|
def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, i128mem:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst,
|
|
(IntId128 VR128:$src1, (memop addr:$src2)))]>,
|
|
OpSize;
|
|
}
|
|
}
|
|
|
|
/// SS48I_binop_rm - Simple SSE41 binary operator.
|
|
let Constraints = "$src1 = $dst" in {
|
|
multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
|
|
ValueType OpVT, bit Commutable = 0> {
|
|
def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
|
|
OpSize {
|
|
let isCommutable = Commutable;
|
|
}
|
|
def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, i128mem:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (OpNode VR128:$src1,
|
|
(bc_v4i32 (memopv2i64 addr:$src2))))]>,
|
|
OpSize;
|
|
}
|
|
}
|
|
|
|
defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, 1>;
|
|
|
|
/// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
|
|
let Constraints = "$src1 = $dst" in {
|
|
multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
|
|
Intrinsic IntId128, bit Commutable = 0> {
|
|
def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
|
[(set VR128:$dst,
|
|
(IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
|
|
OpSize {
|
|
let isCommutable = Commutable;
|
|
}
|
|
def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
|
[(set VR128:$dst,
|
|
(IntId128 VR128:$src1,
|
|
(bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
|
|
OpSize;
|
|
}
|
|
}
|
|
|
|
defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
|
|
int_x86_sse41_blendps, 0>;
|
|
defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
|
|
int_x86_sse41_blendpd, 0>;
|
|
defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
|
|
int_x86_sse41_pblendw, 0>;
|
|
defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
|
|
int_x86_sse41_dpps, 1>;
|
|
defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
|
|
int_x86_sse41_dppd, 1>;
|
|
defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
|
|
int_x86_sse41_mpsadbw, 0>;
|
|
|
|
|
|
/// SS41I_ternary_int - SSE 4.1 ternary operator
|
|
let Uses = [XMM0], Constraints = "$src1 = $dst" in {
|
|
multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
|
|
def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2),
|
|
!strconcat(OpcodeStr,
|
|
"\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
|
|
[(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
|
|
OpSize;
|
|
|
|
def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, i128mem:$src2),
|
|
!strconcat(OpcodeStr,
|
|
"\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
|
|
[(set VR128:$dst,
|
|
(IntId VR128:$src1,
|
|
(bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
|
|
}
|
|
}
|
|
|
|
defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
|
|
defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
|
|
defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
|
|
|
|
|
|
multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
|
|
def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
|
|
|
|
def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst,
|
|
(IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
|
|
OpSize;
|
|
}
|
|
|
|
defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
|
|
defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
|
|
defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
|
|
defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
|
|
defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
|
|
defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
|
|
|
|
// Common patterns involving scalar load.
|
|
def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
|
|
(PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
|
|
def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
|
|
(PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
|
|
|
|
def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
|
|
(PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
|
|
def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
|
|
(PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
|
|
|
|
def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
|
|
(PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
|
|
def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
|
|
(PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
|
|
|
|
def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
|
|
(PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
|
|
def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
|
|
(PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
|
|
|
|
def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
|
|
(PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
|
|
def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
|
|
(PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
|
|
|
|
def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
|
|
(PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
|
|
def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
|
|
(PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
|
|
|
|
|
|
multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
|
|
def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
|
|
|
|
def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst,
|
|
(IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
|
|
OpSize;
|
|
}
|
|
|
|
defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
|
|
defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
|
|
defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
|
|
defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
|
|
|
|
// Common patterns involving scalar load
|
|
def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
|
|
(PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
|
|
def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
|
|
(PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
|
|
|
|
def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
|
|
(PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
|
|
def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
|
|
(PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
|
|
|
|
|
|
multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
|
|
def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
|
|
|
|
// Expecting a i16 load any extended to i32 value.
|
|
def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
|
|
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
|
|
[(set VR128:$dst, (IntId (bitconvert
|
|
(v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
|
|
OpSize;
|
|
}
|
|
|
|
defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
|
|
defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
|
|
|
|
// Common patterns involving scalar load
|
|
def : Pat<(int_x86_sse41_pmovsxbq
|
|
(bitconvert (v4i32 (X86vzmovl
|
|
(v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
|
|
(PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
|
|
|
|
def : Pat<(int_x86_sse41_pmovzxbq
|
|
(bitconvert (v4i32 (X86vzmovl
|
|
(v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
|
|
(PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
|
|
|
|
|
|
/// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
|
|
multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
|
|
def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
|
|
(ins VR128:$src1, i32i8imm:$src2),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
[(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
|
|
OpSize;
|
|
def mr : SS4AIi8<opc, MRMDestMem, (outs),
|
|
(ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
[]>, OpSize;
|
|
// FIXME:
|
|
// There's an AssertZext in the way of writing the store pattern
|
|
// (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
|
|
}
|
|
|
|
defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
|
|
|
|
|
|
/// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
|
|
multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
|
|
def mr : SS4AIi8<opc, MRMDestMem, (outs),
|
|
(ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
[]>, OpSize;
|
|
// FIXME:
|
|
// There's an AssertZext in the way of writing the store pattern
|
|
// (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
|
|
}
|
|
|
|
defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
|
|
|
|
|
|
/// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
|
|
multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
|
|
def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
|
|
(ins VR128:$src1, i32i8imm:$src2),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
[(set GR32:$dst,
|
|
(extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
|
|
def mr : SS4AIi8<opc, MRMDestMem, (outs),
|
|
(ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
[(store (extractelt (v4i32 VR128:$src1), imm:$src2),
|
|
addr:$dst)]>, OpSize;
|
|
}
|
|
|
|
defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
|
|
|
|
|
|
/// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
|
|
/// destination
|
|
multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
|
|
def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
|
|
(ins VR128:$src1, i32i8imm:$src2),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
[(set GR32:$dst,
|
|
(extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
|
|
OpSize;
|
|
def mr : SS4AIi8<opc, MRMDestMem, (outs),
|
|
(ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
|
|
[(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
|
|
addr:$dst)]>, OpSize;
|
|
}
|
|
|
|
defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
|
|
|
|
// Also match an EXTRACTPS store when the store is done as f32 instead of i32.
|
|
def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
|
|
imm:$src2))),
|
|
addr:$dst),
|
|
(EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
|
|
Requires<[HasSSE41]>;
|
|
|
|
let Constraints = "$src1 = $dst" in {
|
|
multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
|
|
def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
|
[(set VR128:$dst,
|
|
(X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
|
|
def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
|
[(set VR128:$dst,
|
|
(X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
|
|
imm:$src3))]>, OpSize;
|
|
}
|
|
}
|
|
|
|
defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
|
|
|
|
let Constraints = "$src1 = $dst" in {
|
|
multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
|
|
def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
|
[(set VR128:$dst,
|
|
(v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
|
|
OpSize;
|
|
def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
|
[(set VR128:$dst,
|
|
(v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
|
|
imm:$src3)))]>, OpSize;
|
|
}
|
|
}
|
|
|
|
defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
|
|
|
|
// insertps has a few different modes, there's the first two here below which
|
|
// are optimized inserts that won't zero arbitrary elements in the destination
|
|
// vector. The next one matches the intrinsic and could zero arbitrary elements
|
|
// in the target vector.
|
|
let Constraints = "$src1 = $dst" in {
|
|
multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
|
|
def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
|
[(set VR128:$dst,
|
|
(X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
|
|
OpSize;
|
|
def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
|
[(set VR128:$dst,
|
|
(X86insrtps VR128:$src1,
|
|
(v4f32 (scalar_to_vector (loadf32 addr:$src2))),
|
|
imm:$src3))]>, OpSize;
|
|
}
|
|
}
|
|
|
|
defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
|
|
|
|
def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
|
|
(INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
|
|
|
|
// ptest instruction we'll lower to this in X86ISelLowering primarily from
|
|
// the intel intrinsic that corresponds to this.
|
|
let Defs = [EFLAGS] in {
|
|
def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
|
|
"ptest \t{$src2, $src1|$src1, $src2}",
|
|
[(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
|
|
OpSize;
|
|
def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
|
|
"ptest \t{$src2, $src1|$src1, $src2}",
|
|
[(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
|
|
OpSize;
|
|
}
|
|
|
|
def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
|
|
"movntdqa\t{$src, $dst|$dst, $src}",
|
|
[(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
|
|
OpSize;
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// SSE4.2 Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
|
|
let Constraints = "$src1 = $dst" in {
|
|
multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
|
|
Intrinsic IntId128, bit Commutable = 0> {
|
|
def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
|
|
OpSize {
|
|
let isCommutable = Commutable;
|
|
}
|
|
def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, i128mem:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst,
|
|
(IntId128 VR128:$src1,
|
|
(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
|
|
}
|
|
}
|
|
|
|
defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
|
|
|
|
def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
|
|
(PCMPGTQrr VR128:$src1, VR128:$src2)>;
|
|
def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
|
|
(PCMPGTQrm VR128:$src1, addr:$src2)>;
|
|
|
|
// crc intrinsic instruction
|
|
// This set of instructions are only rm, the only difference is the size
|
|
// of r and m.
|
|
let Constraints = "$src1 = $dst" in {
|
|
def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
|
|
(ins GR32:$src1, i8mem:$src2),
|
|
"crc32{b} \t{$src2, $src1|$src1, $src2}",
|
|
[(set GR32:$dst,
|
|
(int_x86_sse42_crc32_8 GR32:$src1,
|
|
(load addr:$src2)))]>;
|
|
def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
|
|
(ins GR32:$src1, GR8:$src2),
|
|
"crc32{b} \t{$src2, $src1|$src1, $src2}",
|
|
[(set GR32:$dst,
|
|
(int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
|
|
def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
|
|
(ins GR32:$src1, i16mem:$src2),
|
|
"crc32{w} \t{$src2, $src1|$src1, $src2}",
|
|
[(set GR32:$dst,
|
|
(int_x86_sse42_crc32_16 GR32:$src1,
|
|
(load addr:$src2)))]>,
|
|
OpSize;
|
|
def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
|
|
(ins GR32:$src1, GR16:$src2),
|
|
"crc32{w} \t{$src2, $src1|$src1, $src2}",
|
|
[(set GR32:$dst,
|
|
(int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
|
|
OpSize;
|
|
def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
|
|
(ins GR32:$src1, i32mem:$src2),
|
|
"crc32{l} \t{$src2, $src1|$src1, $src2}",
|
|
[(set GR32:$dst,
|
|
(int_x86_sse42_crc32_32 GR32:$src1,
|
|
(load addr:$src2)))]>;
|
|
def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
|
|
(ins GR32:$src1, GR32:$src2),
|
|
"crc32{l} \t{$src2, $src1|$src1, $src2}",
|
|
[(set GR32:$dst,
|
|
(int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
|
|
def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
|
|
(ins GR64:$src1, i8mem:$src2),
|
|
"crc32{b} \t{$src2, $src1|$src1, $src2}",
|
|
[(set GR64:$dst,
|
|
(int_x86_sse42_crc64_8 GR64:$src1,
|
|
(load addr:$src2)))]>,
|
|
REX_W;
|
|
def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
|
|
(ins GR64:$src1, GR8:$src2),
|
|
"crc32{b} \t{$src2, $src1|$src1, $src2}",
|
|
[(set GR64:$dst,
|
|
(int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
|
|
REX_W;
|
|
def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
|
|
(ins GR64:$src1, i64mem:$src2),
|
|
"crc32{q} \t{$src2, $src1|$src1, $src2}",
|
|
[(set GR64:$dst,
|
|
(int_x86_sse42_crc64_64 GR64:$src1,
|
|
(load addr:$src2)))]>,
|
|
REX_W;
|
|
def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
|
|
(ins GR64:$src1, GR64:$src2),
|
|
"crc32{q} \t{$src2, $src1|$src1, $src2}",
|
|
[(set GR64:$dst,
|
|
(int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
|
|
REX_W;
|
|
}
|
|
|
|
// String/text processing instructions.
|
|
let Defs = [EFLAGS], usesCustomInserter = 1 in {
|
|
def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2, i8imm:$src3),
|
|
"#PCMPISTRM128rr PSEUDO!",
|
|
[(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
|
|
imm:$src3))]>, OpSize;
|
|
def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
|
|
(ins VR128:$src1, i128mem:$src2, i8imm:$src3),
|
|
"#PCMPISTRM128rm PSEUDO!",
|
|
[(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, (load addr:$src2),
|
|
imm:$src3))]>, OpSize;
|
|
}
|
|
|
|
let Defs = [XMM0, EFLAGS] in {
|
|
def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
|
|
(ins VR128:$src1, VR128:$src2, i8imm:$src3),
|
|
"pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
|
|
def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
|
|
(ins VR128:$src1, i128mem:$src2, i8imm:$src3),
|
|
"pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
|
|
}
|
|
|
|
let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
|
|
def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src3, i8imm:$src5),
|
|
"#PCMPESTRM128rr PSEUDO!",
|
|
[(set VR128:$dst,
|
|
(int_x86_sse42_pcmpestrm128
|
|
VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
|
|
|
|
def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
|
|
(ins VR128:$src1, i128mem:$src3, i8imm:$src5),
|
|
"#PCMPESTRM128rm PSEUDO!",
|
|
[(set VR128:$dst, (int_x86_sse42_pcmpestrm128
|
|
VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
|
|
OpSize;
|
|
}
|
|
|
|
let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
|
|
def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
|
|
(ins VR128:$src1, VR128:$src3, i8imm:$src5),
|
|
"pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
|
|
def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
|
|
(ins VR128:$src1, i128mem:$src3, i8imm:$src5),
|
|
"pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
|
|
}
|
|
|
|
let Defs = [ECX, EFLAGS] in {
|
|
multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
|
|
def rr : SS42AI<0x63, MRMSrcReg, (outs),
|
|
(ins VR128:$src1, VR128:$src2, i8imm:$src3),
|
|
"pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
|
|
[(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
|
|
(implicit EFLAGS)]>, OpSize;
|
|
def rm : SS42AI<0x63, MRMSrcMem, (outs),
|
|
(ins VR128:$src1, i128mem:$src2, i8imm:$src3),
|
|
"pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
|
|
[(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
|
|
(implicit EFLAGS)]>, OpSize;
|
|
}
|
|
}
|
|
|
|
defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
|
|
defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
|
|
defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
|
|
defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
|
|
defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
|
|
defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
|
|
|
|
let Defs = [ECX, EFLAGS] in {
|
|
let Uses = [EAX, EDX] in {
|
|
multiclass SS42AI_pcmpestri<Intrinsic IntId128> {
|
|
def rr : SS42AI<0x61, MRMSrcReg, (outs),
|
|
(ins VR128:$src1, VR128:$src3, i8imm:$src5),
|
|
"pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
|
|
[(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
|
|
(implicit EFLAGS)]>, OpSize;
|
|
def rm : SS42AI<0x61, MRMSrcMem, (outs),
|
|
(ins VR128:$src1, i128mem:$src3, i8imm:$src5),
|
|
"pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
|
|
[(set ECX,
|
|
(IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
|
|
(implicit EFLAGS)]>, OpSize;
|
|
}
|
|
}
|
|
}
|
|
|
|
defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
|
|
defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
|
|
defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
|
|
defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
|
|
defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
|
|
defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// AES-NI Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let Constraints = "$src1 = $dst" in {
|
|
multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
|
|
Intrinsic IntId128, bit Commutable = 0> {
|
|
def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
|
|
OpSize {
|
|
let isCommutable = Commutable;
|
|
}
|
|
def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, i128mem:$src2),
|
|
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
|
[(set VR128:$dst,
|
|
(IntId128 VR128:$src1,
|
|
(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
|
|
}
|
|
}
|
|
|
|
defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
|
|
int_x86_aesni_aesenc>;
|
|
defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
|
|
int_x86_aesni_aesenclast>;
|
|
defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
|
|
int_x86_aesni_aesdec>;
|
|
defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
|
|
int_x86_aesni_aesdeclast>;
|
|
|
|
def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
|
|
(AESENCrr VR128:$src1, VR128:$src2)>;
|
|
def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
|
|
(AESENCrm VR128:$src1, addr:$src2)>;
|
|
def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
|
|
(AESENCLASTrr VR128:$src1, VR128:$src2)>;
|
|
def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
|
|
(AESENCLASTrm VR128:$src1, addr:$src2)>;
|
|
def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
|
|
(AESDECrr VR128:$src1, VR128:$src2)>;
|
|
def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
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(AESDECrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
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(AESDECLASTrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
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(AESDECLASTrm VR128:$src1, addr:$src2)>;
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def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1),
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"aesimc\t{$src1, $dst|$dst, $src1}",
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[(set VR128:$dst,
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(int_x86_aesni_aesimc VR128:$src1))]>,
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OpSize;
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def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
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(ins i128mem:$src1),
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"aesimc\t{$src1, $dst|$dst, $src1}",
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[(set VR128:$dst,
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(int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
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OpSize;
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def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, i8imm:$src2),
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"aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst,
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(int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
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OpSize;
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def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
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(ins i128mem:$src1, i8imm:$src2),
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"aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR128:$dst,
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(int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
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imm:$src2))]>,
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OpSize;
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