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https://github.com/c64scene-ar/llvm-6502.git
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c0b0c677a1
Only implemented for R600 so far. SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.
At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.
v2:
- Add support for i8 zext load from stack.
- Coding style fixes
v3:
- Don't reserve registers for indirect addressing when it isn't
being used.
- Fix bug caused by LLVM limiting the number of SubRegIndex
declarations.
v4:
- Fix 64-bit defines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174525 91177308-0d34-0410-b5e6-96231b3b80d8
83 lines
2.7 KiB
TableGen
83 lines
2.7 KiB
TableGen
//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains DAG node defintions for the AMDGPU target.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// AMDGPU DAG Profiles
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//===----------------------------------------------------------------------===//
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def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
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SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
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]>;
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//===----------------------------------------------------------------------===//
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// AMDGPU DAG Nodes
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//
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// out = ((a << 32) | b) >> c)
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//
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// Can be used to optimize rtol:
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// rotl(a, b) = bitalign(a, a, 32 - b)
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def AMDGPUbitalign : SDNode<"AMDGPUISD::BITALIGN", AMDGPUDTIntTernaryOp>;
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// This argument to this node is a dword address.
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def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
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// out = a - floor(a)
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def AMDGPUfract : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
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// out = max(a, b) a and b are floats
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def AMDGPUfmax : SDNode<"AMDGPUISD::FMAX", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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// out = max(a, b) a and b are signed ints
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def AMDGPUsmax : SDNode<"AMDGPUISD::SMAX", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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// out = max(a, b) a and b are unsigned ints
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def AMDGPUumax : SDNode<"AMDGPUISD::UMAX", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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// out = min(a, b) a and b are floats
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def AMDGPUfmin : SDNode<"AMDGPUISD::FMIN", SDTFPBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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// out = min(a, b) a snd b are signed ints
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def AMDGPUsmin : SDNode<"AMDGPUISD::SMIN", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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// out = min(a, b) a and b are unsigned ints
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def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,
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[SDNPCommutative, SDNPAssociative]
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>;
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// urecip - This operation is a helper for integer division, it returns the
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// result of 1 / a as a fractional unsigned integer.
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// out = (2^32 / a) + e
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// e is rounding error
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def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
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def fpow : SDNode<"ISD::FPOW", SDTFPBinOp>;
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def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
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SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
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[SDNPHasChain, SDNPMayLoad]>;
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def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
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SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
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[SDNPHasChain, SDNPMayStore]>;
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