llvm-6502/test/CodeGen
Michael Liao f8fd883fd3 Add XTEST codegen support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-26 22:47:01 +00:00
..
AArch64 Update PEI's virtual-register-based scavenging to support multiple simultaneous mappings 2013-03-26 18:56:54 +00:00
ARM
CPP
Generic
Hexagon Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth. 2013-03-26 15:43:57 +00:00
Inputs
MBlaze
Mips
MSP430
NVPTX
PowerPC Use multiple virtual registers in PPC CR spilling 2013-03-26 18:57:22 +00:00
R600
SI
SPARC
Thumb
Thumb2
X86 Add XTEST codegen support 2013-03-26 22:47:01 +00:00
XCore