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966e6ca1ac
DataLayout is no longer optional. It was initialized with or without a DataLayout, and the DataLayout when supplied could have been the one from the TargetMachine. Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: jholewinski, llvm-commits, rafael, yaron.keren Differential Revision: http://reviews.llvm.org/D11021 From: Mehdi Amini <mehdi.amini@apple.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241774 91177308-0d34-0410-b5e6-96231b3b80d8
129 lines
3.9 KiB
C++
129 lines
3.9 KiB
C++
//===-- ARMTargetTransformInfo.h - ARM specific TTI -------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file a TargetTransformInfo::Concept conforming object specific to the
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/// ARM target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
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#include "ARM.h"
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#include "ARMTargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
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typedef BasicTTIImplBase<ARMTTIImpl> BaseT;
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typedef TargetTransformInfo TTI;
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friend BaseT;
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const ARMSubtarget *ST;
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const ARMTargetLowering *TLI;
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/// Estimate the overhead of scalarizing an instruction. Insert and Extract
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/// are set if the result needs to be inserted and/or extracted from vectors.
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unsigned getScalarizationOverhead(Type *Ty, bool Insert, bool Extract);
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const ARMSubtarget *getST() const { return ST; }
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const ARMTargetLowering *getTLI() const { return TLI; }
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public:
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explicit ARMTTIImpl(const ARMBaseTargetMachine *TM, Function &F)
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: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()) {}
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// Provide value semantics. MSVC requires that we spell all of these out.
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ARMTTIImpl(const ARMTTIImpl &Arg)
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: BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {}
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ARMTTIImpl(ARMTTIImpl &&Arg)
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: BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)),
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TLI(std::move(Arg.TLI)) {}
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/// \name Scalar TTI Implementations
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/// @{
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using BaseT::getIntImmCost;
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unsigned getIntImmCost(const APInt &Imm, Type *Ty);
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/// @}
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/// \name Vector TTI Implementations
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/// @{
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unsigned getNumberOfRegisters(bool Vector) {
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if (Vector) {
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if (ST->hasNEON())
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return 16;
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return 0;
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}
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if (ST->isThumb1Only())
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return 8;
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return 13;
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}
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unsigned getRegisterBitWidth(bool Vector) {
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if (Vector) {
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if (ST->hasNEON())
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return 128;
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return 0;
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}
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return 32;
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}
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unsigned getMaxInterleaveFactor(unsigned VF) {
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// These are out of order CPUs:
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if (ST->isCortexA15() || ST->isSwift())
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return 2;
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return 1;
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}
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unsigned getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index,
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Type *SubTp);
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unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src);
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unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy);
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unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
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unsigned getAddressComputationCost(Type *Val, bool IsComplex);
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unsigned getFPOpCost(Type *Ty);
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unsigned getArithmeticInstrCost(
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unsigned Opcode, Type *Ty,
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TTI::OperandValueKind Op1Info = TTI::OK_AnyValue,
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TTI::OperandValueKind Op2Info = TTI::OK_AnyValue,
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TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
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TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
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unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
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unsigned AddressSpace);
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unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
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unsigned Factor,
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ArrayRef<unsigned> Indices,
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unsigned Alignment,
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unsigned AddressSpace);
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/// @}
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};
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} // end namespace llvm
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#endif
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