mirror of
https://github.com/c64scene-ar/llvm-6502.git
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f29cc18dcb
Summary: This change is part of a series of commits dedicated to have a single DataLayout during compilation by using always the one owned by the module. Reviewers: echristo Subscribers: jholewinski, ted, yaron.keren, rafael, llvm-commits Differential Revision: http://reviews.llvm.org/D11028 From: Mehdi Amini <mehdi.amini@apple.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241775 91177308-0d34-0410-b5e6-96231b3b80d8
490 lines
15 KiB
C++
490 lines
15 KiB
C++
//===-- MSP430ISelDAGToDAG.cpp - A dag to dag inst selector for MSP430 ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the MSP430 target.
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//
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//===----------------------------------------------------------------------===//
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#include "MSP430.h"
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#include "MSP430TargetMachine.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetLowering.h"
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using namespace llvm;
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#define DEBUG_TYPE "msp430-isel"
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namespace {
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struct MSP430ISelAddressMode {
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enum {
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RegBase,
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FrameIndexBase
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} BaseType;
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struct { // This is really a union, discriminated by BaseType!
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SDValue Reg;
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int FrameIndex;
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} Base;
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int16_t Disp;
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const GlobalValue *GV;
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const Constant *CP;
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const BlockAddress *BlockAddr;
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const char *ES;
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int JT;
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unsigned Align; // CP alignment.
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MSP430ISelAddressMode()
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: BaseType(RegBase), Disp(0), GV(nullptr), CP(nullptr),
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BlockAddr(nullptr), ES(nullptr), JT(-1), Align(0) {
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}
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bool hasSymbolicDisplacement() const {
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return GV != nullptr || CP != nullptr || ES != nullptr || JT != -1;
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}
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void dump() {
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errs() << "MSP430ISelAddressMode " << this << '\n';
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if (BaseType == RegBase && Base.Reg.getNode() != nullptr) {
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errs() << "Base.Reg ";
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Base.Reg.getNode()->dump();
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} else if (BaseType == FrameIndexBase) {
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errs() << " Base.FrameIndex " << Base.FrameIndex << '\n';
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}
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errs() << " Disp " << Disp << '\n';
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if (GV) {
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errs() << "GV ";
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GV->dump();
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} else if (CP) {
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errs() << " CP ";
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CP->dump();
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errs() << " Align" << Align << '\n';
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} else if (ES) {
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errs() << "ES ";
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errs() << ES << '\n';
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} else if (JT != -1)
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errs() << " JT" << JT << " Align" << Align << '\n';
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}
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};
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}
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/// MSP430DAGToDAGISel - MSP430 specific code to select MSP430 machine
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/// instructions for SelectionDAG operations.
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///
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namespace {
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class MSP430DAGToDAGISel : public SelectionDAGISel {
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public:
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MSP430DAGToDAGISel(MSP430TargetMachine &TM, CodeGenOpt::Level OptLevel)
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: SelectionDAGISel(TM, OptLevel) {}
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const char *getPassName() const override {
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return "MSP430 DAG->DAG Pattern Instruction Selection";
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}
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bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
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bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
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bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
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bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
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std::vector<SDValue> &OutOps) override;
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// Include the pieces autogenerated from the target description.
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#include "MSP430GenDAGISel.inc"
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private:
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SDNode *Select(SDNode *N) override;
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SDNode *SelectIndexedLoad(SDNode *Op);
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SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
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unsigned Opc8, unsigned Opc16);
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bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
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};
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} // end anonymous namespace
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/// createMSP430ISelDag - This pass converts a legalized DAG into a
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/// MSP430-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createMSP430ISelDag(MSP430TargetMachine &TM,
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CodeGenOpt::Level OptLevel) {
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return new MSP430DAGToDAGISel(TM, OptLevel);
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}
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/// MatchWrapper - Try to match MSP430ISD::Wrapper node into an addressing mode.
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/// These wrap things that will resolve down into a symbol reference. If no
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/// match is possible, this returns true, otherwise it returns false.
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bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) {
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// If the addressing mode already has a symbol as the displacement, we can
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// never match another symbol.
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if (AM.hasSymbolicDisplacement())
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return true;
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SDValue N0 = N.getOperand(0);
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
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AM.GV = G->getGlobal();
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AM.Disp += G->getOffset();
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//AM.SymbolFlags = G->getTargetFlags();
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} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
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AM.CP = CP->getConstVal();
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AM.Align = CP->getAlignment();
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AM.Disp += CP->getOffset();
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//AM.SymbolFlags = CP->getTargetFlags();
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} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
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AM.ES = S->getSymbol();
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//AM.SymbolFlags = S->getTargetFlags();
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} else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
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AM.JT = J->getIndex();
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//AM.SymbolFlags = J->getTargetFlags();
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} else {
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AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
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//AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
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}
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return false;
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}
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/// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
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/// specified addressing mode without any further recursion.
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bool MSP430DAGToDAGISel::MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM) {
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// Is the base register already occupied?
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if (AM.BaseType != MSP430ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
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// If so, we cannot select it.
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return true;
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}
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// Default, generate it as a register.
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AM.BaseType = MSP430ISelAddressMode::RegBase;
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AM.Base.Reg = N;
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return false;
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}
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bool MSP430DAGToDAGISel::MatchAddress(SDValue N, MSP430ISelAddressMode &AM) {
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DEBUG(errs() << "MatchAddress: "; AM.dump());
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switch (N.getOpcode()) {
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default: break;
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case ISD::Constant: {
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uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
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AM.Disp += Val;
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return false;
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}
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case MSP430ISD::Wrapper:
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if (!MatchWrapper(N, AM))
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return false;
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break;
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case ISD::FrameIndex:
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if (AM.BaseType == MSP430ISelAddressMode::RegBase
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&& AM.Base.Reg.getNode() == nullptr) {
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AM.BaseType = MSP430ISelAddressMode::FrameIndexBase;
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AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
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return false;
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}
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break;
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case ISD::ADD: {
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MSP430ISelAddressMode Backup = AM;
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if (!MatchAddress(N.getNode()->getOperand(0), AM) &&
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!MatchAddress(N.getNode()->getOperand(1), AM))
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return false;
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AM = Backup;
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if (!MatchAddress(N.getNode()->getOperand(1), AM) &&
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!MatchAddress(N.getNode()->getOperand(0), AM))
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return false;
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AM = Backup;
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break;
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}
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case ISD::OR:
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// Handle "X | C" as "X + C" iff X is known to have C bits clear.
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
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MSP430ISelAddressMode Backup = AM;
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uint64_t Offset = CN->getSExtValue();
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// Start with the LHS as an addr mode.
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if (!MatchAddress(N.getOperand(0), AM) &&
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// Address could not have picked a GV address for the displacement.
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AM.GV == nullptr &&
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// Check to see if the LHS & C is zero.
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CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
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AM.Disp += Offset;
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return false;
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}
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AM = Backup;
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}
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break;
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}
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return MatchAddressBase(N, AM);
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}
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/// SelectAddr - returns true if it is able pattern match an addressing mode.
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/// It returns the operands which make up the maximal addressing mode it can
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/// match by reference.
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bool MSP430DAGToDAGISel::SelectAddr(SDValue N,
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SDValue &Base, SDValue &Disp) {
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MSP430ISelAddressMode AM;
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if (MatchAddress(N, AM))
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return false;
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EVT VT = N.getValueType();
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if (AM.BaseType == MSP430ISelAddressMode::RegBase) {
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if (!AM.Base.Reg.getNode())
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AM.Base.Reg = CurDAG->getRegister(0, VT);
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}
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Base = (AM.BaseType == MSP430ISelAddressMode::FrameIndexBase)
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? CurDAG->getTargetFrameIndex(
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AM.Base.FrameIndex,
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getTargetLowering()->getPointerTy(CurDAG->getDataLayout()))
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: AM.Base.Reg;
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if (AM.GV)
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Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(N),
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MVT::i16, AM.Disp,
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0/*AM.SymbolFlags*/);
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else if (AM.CP)
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Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16,
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AM.Align, AM.Disp, 0/*AM.SymbolFlags*/);
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else if (AM.ES)
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Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/);
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else if (AM.JT != -1)
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Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i16, 0/*AM.SymbolFlags*/);
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else if (AM.BlockAddr)
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Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, 0,
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0/*AM.SymbolFlags*/);
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else
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Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(N), MVT::i16);
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return true;
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}
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bool MSP430DAGToDAGISel::
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SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
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std::vector<SDValue> &OutOps) {
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SDValue Op0, Op1;
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switch (ConstraintID) {
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default: return true;
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case InlineAsm::Constraint_m: // memory
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if (!SelectAddr(Op, Op0, Op1))
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return true;
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break;
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}
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OutOps.push_back(Op0);
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OutOps.push_back(Op1);
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return false;
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}
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static bool isValidIndexedLoad(const LoadSDNode *LD) {
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ISD::MemIndexedMode AM = LD->getAddressingMode();
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if (AM != ISD::POST_INC || LD->getExtensionType() != ISD::NON_EXTLOAD)
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return false;
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EVT VT = LD->getMemoryVT();
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switch (VT.getSimpleVT().SimpleTy) {
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case MVT::i8:
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// Sanity check
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if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 1)
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return false;
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break;
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case MVT::i16:
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// Sanity check
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if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 2)
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return false;
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break;
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default:
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return false;
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}
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return true;
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}
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SDNode *MSP430DAGToDAGISel::SelectIndexedLoad(SDNode *N) {
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LoadSDNode *LD = cast<LoadSDNode>(N);
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if (!isValidIndexedLoad(LD))
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return nullptr;
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MVT VT = LD->getMemoryVT().getSimpleVT();
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unsigned Opcode = 0;
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switch (VT.SimpleTy) {
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case MVT::i8:
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Opcode = MSP430::MOV8rm_POST;
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break;
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case MVT::i16:
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Opcode = MSP430::MOV16rm_POST;
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break;
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default:
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return nullptr;
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}
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return CurDAG->getMachineNode(Opcode, SDLoc(N),
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VT, MVT::i16, MVT::Other,
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LD->getBasePtr(), LD->getChain());
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}
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SDNode *MSP430DAGToDAGISel::SelectIndexedBinOp(SDNode *Op,
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SDValue N1, SDValue N2,
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unsigned Opc8, unsigned Opc16) {
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if (N1.getOpcode() == ISD::LOAD &&
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N1.hasOneUse() &&
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IsLegalToFold(N1, Op, Op, OptLevel)) {
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LoadSDNode *LD = cast<LoadSDNode>(N1);
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if (!isValidIndexedLoad(LD))
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return nullptr;
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MVT VT = LD->getMemoryVT().getSimpleVT();
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unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
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MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
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MemRefs0[0] = cast<MemSDNode>(N1)->getMemOperand();
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SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() };
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SDNode *ResNode =
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CurDAG->SelectNodeTo(Op, Opc, VT, MVT::i16, MVT::Other, Ops0);
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cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1);
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// Transfer chain.
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ReplaceUses(SDValue(N1.getNode(), 2), SDValue(ResNode, 2));
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// Transfer writeback.
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ReplaceUses(SDValue(N1.getNode(), 1), SDValue(ResNode, 1));
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return ResNode;
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}
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return nullptr;
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}
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SDNode *MSP430DAGToDAGISel::Select(SDNode *Node) {
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SDLoc dl(Node);
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// Dump information about the Node being selected
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DEBUG(errs() << "Selecting: ");
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DEBUG(Node->dump(CurDAG));
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DEBUG(errs() << "\n");
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// If we have a custom node, we already have selected!
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if (Node->isMachineOpcode()) {
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DEBUG(errs() << "== ";
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Node->dump(CurDAG);
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errs() << "\n");
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Node->setNodeId(-1);
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return nullptr;
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}
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// Few custom selection stuff.
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switch (Node->getOpcode()) {
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default: break;
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case ISD::FrameIndex: {
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assert(Node->getValueType(0) == MVT::i16);
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int FI = cast<FrameIndexSDNode>(Node)->getIndex();
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SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16);
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if (Node->hasOneUse())
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return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, MVT::i16, TFI,
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CurDAG->getTargetConstant(0, dl, MVT::i16));
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return CurDAG->getMachineNode(MSP430::ADD16ri, dl, MVT::i16, TFI,
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CurDAG->getTargetConstant(0, dl, MVT::i16));
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}
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case ISD::LOAD:
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if (SDNode *ResNode = SelectIndexedLoad(Node))
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return ResNode;
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// Other cases are autogenerated.
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break;
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case ISD::ADD:
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if (SDNode *ResNode =
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SelectIndexedBinOp(Node,
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Node->getOperand(0), Node->getOperand(1),
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MSP430::ADD8rm_POST, MSP430::ADD16rm_POST))
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return ResNode;
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else if (SDNode *ResNode =
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SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
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MSP430::ADD8rm_POST, MSP430::ADD16rm_POST))
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return ResNode;
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// Other cases are autogenerated.
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break;
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case ISD::SUB:
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if (SDNode *ResNode =
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SelectIndexedBinOp(Node,
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Node->getOperand(0), Node->getOperand(1),
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MSP430::SUB8rm_POST, MSP430::SUB16rm_POST))
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return ResNode;
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// Other cases are autogenerated.
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break;
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case ISD::AND:
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if (SDNode *ResNode =
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SelectIndexedBinOp(Node,
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Node->getOperand(0), Node->getOperand(1),
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MSP430::AND8rm_POST, MSP430::AND16rm_POST))
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return ResNode;
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else if (SDNode *ResNode =
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SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
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MSP430::AND8rm_POST, MSP430::AND16rm_POST))
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return ResNode;
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// Other cases are autogenerated.
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break;
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case ISD::OR:
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if (SDNode *ResNode =
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SelectIndexedBinOp(Node,
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Node->getOperand(0), Node->getOperand(1),
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MSP430::OR8rm_POST, MSP430::OR16rm_POST))
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return ResNode;
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else if (SDNode *ResNode =
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SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
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MSP430::OR8rm_POST, MSP430::OR16rm_POST))
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return ResNode;
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// Other cases are autogenerated.
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break;
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case ISD::XOR:
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if (SDNode *ResNode =
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SelectIndexedBinOp(Node,
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Node->getOperand(0), Node->getOperand(1),
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MSP430::XOR8rm_POST, MSP430::XOR16rm_POST))
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return ResNode;
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else if (SDNode *ResNode =
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SelectIndexedBinOp(Node, Node->getOperand(1), Node->getOperand(0),
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MSP430::XOR8rm_POST, MSP430::XOR16rm_POST))
|
|
return ResNode;
|
|
|
|
// Other cases are autogenerated.
|
|
break;
|
|
}
|
|
|
|
// Select the default instruction
|
|
SDNode *ResNode = SelectCode(Node);
|
|
|
|
DEBUG(errs() << "=> ");
|
|
if (ResNode == nullptr || ResNode == Node)
|
|
DEBUG(Node->dump(CurDAG));
|
|
else
|
|
DEBUG(ResNode->dump(CurDAG));
|
|
DEBUG(errs() << "\n");
|
|
|
|
return ResNode;
|
|
}
|