mirror of
https://github.com/c64scene-ar/llvm-6502.git
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e143a3abc2
These directives are used to set the default value of the SoftFloat feature.
They have the same effect as setting -m{soft, hard}-float from the command line.
Differential Revision: http://reviews.llvm.org/D9073
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241066 91177308-0d34-0410-b5e6-96231b3b80d8
825 lines
28 KiB
C++
825 lines
28 KiB
C++
//===-- MipsTargetStreamer.cpp - Mips Target Streamer Methods -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides Mips specific target streamer methods.
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//
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//===----------------------------------------------------------------------===//
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#include "InstPrinter/MipsInstPrinter.h"
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#include "MipsELFStreamer.h"
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#include "MipsMCTargetDesc.h"
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#include "MipsTargetObjectFile.h"
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#include "MipsTargetStreamer.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbolELF.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ELF.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormattedStream.h"
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using namespace llvm;
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MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S)
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: MCTargetStreamer(S), ModuleDirectiveAllowed(true) {
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GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
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}
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void MipsTargetStreamer::emitDirectiveSetMicroMips() {}
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void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {}
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void MipsTargetStreamer::emitDirectiveSetMips16() {}
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void MipsTargetStreamer::emitDirectiveSetNoMips16() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetNoReorder() {}
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void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
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forbidModuleDirective();
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}
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void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {}
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void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {}
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void MipsTargetStreamer::emitDirectiveAbiCalls() {}
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void MipsTargetStreamer::emitDirectiveNaN2008() {}
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void MipsTargetStreamer::emitDirectiveNaNLegacy() {}
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void MipsTargetStreamer::emitDirectiveOptionPic0() {}
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void MipsTargetStreamer::emitDirectiveOptionPic2() {}
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void MipsTargetStreamer::emitDirectiveInsn() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
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unsigned ReturnReg) {}
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void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {}
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void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) {
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}
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void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) {
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forbidModuleDirective();
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}
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void MipsTargetStreamer::emitDirectiveSetMips0() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetMips32R3() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetMips32R5() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetMips64R3() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetMips64R5() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetPop() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetPush() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetSoftFloat() {
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forbidModuleDirective();
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}
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void MipsTargetStreamer::emitDirectiveSetHardFloat() {
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forbidModuleDirective();
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}
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void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {}
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void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
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const MCSymbol &Sym, bool IsReg) {
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}
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void MipsTargetStreamer::emitDirectiveModuleFP() {}
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void MipsTargetStreamer::emitDirectiveModuleOddSPReg() {
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if (!ABIFlagsSection.OddSPReg && !ABIFlagsSection.Is32BitABI)
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report_fatal_error("+nooddspreg is only valid for O32");
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}
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void MipsTargetStreamer::emitDirectiveModuleSoftFloat() {}
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void MipsTargetStreamer::emitDirectiveModuleHardFloat() {}
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void MipsTargetStreamer::emitDirectiveSetFp(
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MipsABIFlagsSection::FpABIKind Value) {
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forbidModuleDirective();
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}
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void MipsTargetStreamer::emitDirectiveSetOddSPReg() { forbidModuleDirective(); }
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void MipsTargetStreamer::emitDirectiveSetNoOddSPReg() {
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forbidModuleDirective();
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}
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MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S,
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formatted_raw_ostream &OS)
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: MipsTargetStreamer(S), OS(OS) {}
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void MipsTargetAsmStreamer::emitDirectiveSetMicroMips() {
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OS << "\t.set\tmicromips\n";
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forbidModuleDirective();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetNoMicroMips() {
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OS << "\t.set\tnomicromips\n";
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forbidModuleDirective();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetMips16() {
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OS << "\t.set\tmips16\n";
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forbidModuleDirective();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetNoMips16() {
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OS << "\t.set\tnomips16\n";
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MipsTargetStreamer::emitDirectiveSetNoMips16();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetReorder() {
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OS << "\t.set\treorder\n";
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MipsTargetStreamer::emitDirectiveSetReorder();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetNoReorder() {
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OS << "\t.set\tnoreorder\n";
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forbidModuleDirective();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetMacro() {
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OS << "\t.set\tmacro\n";
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MipsTargetStreamer::emitDirectiveSetMacro();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetNoMacro() {
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OS << "\t.set\tnomacro\n";
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MipsTargetStreamer::emitDirectiveSetNoMacro();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetMsa() {
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OS << "\t.set\tmsa\n";
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MipsTargetStreamer::emitDirectiveSetMsa();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetNoMsa() {
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OS << "\t.set\tnomsa\n";
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MipsTargetStreamer::emitDirectiveSetNoMsa();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetAt() {
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OS << "\t.set\tat\n";
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MipsTargetStreamer::emitDirectiveSetAt();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetAtWithArg(unsigned RegNo) {
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OS << "\t.set\tat=$" << Twine(RegNo) << "\n";
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MipsTargetStreamer::emitDirectiveSetAtWithArg(RegNo);
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}
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void MipsTargetAsmStreamer::emitDirectiveSetNoAt() {
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OS << "\t.set\tnoat\n";
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MipsTargetStreamer::emitDirectiveSetNoAt();
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}
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void MipsTargetAsmStreamer::emitDirectiveEnd(StringRef Name) {
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OS << "\t.end\t" << Name << '\n';
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}
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void MipsTargetAsmStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
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OS << "\t.ent\t" << Symbol.getName() << '\n';
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}
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void MipsTargetAsmStreamer::emitDirectiveAbiCalls() { OS << "\t.abicalls\n"; }
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void MipsTargetAsmStreamer::emitDirectiveNaN2008() { OS << "\t.nan\t2008\n"; }
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void MipsTargetAsmStreamer::emitDirectiveNaNLegacy() {
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OS << "\t.nan\tlegacy\n";
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}
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void MipsTargetAsmStreamer::emitDirectiveOptionPic0() {
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OS << "\t.option\tpic0\n";
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}
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void MipsTargetAsmStreamer::emitDirectiveOptionPic2() {
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OS << "\t.option\tpic2\n";
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}
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void MipsTargetAsmStreamer::emitDirectiveInsn() {
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MipsTargetStreamer::emitDirectiveInsn();
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OS << "\t.insn\n";
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}
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void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
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unsigned ReturnReg) {
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OS << "\t.frame\t$"
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<< StringRef(MipsInstPrinter::getRegisterName(StackReg)).lower() << ","
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<< StackSize << ",$"
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<< StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n';
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}
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void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) {
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OS << "\t.set arch=" << Arch << "\n";
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MipsTargetStreamer::emitDirectiveSetArch(Arch);
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}
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void MipsTargetAsmStreamer::emitDirectiveSetMips0() {
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OS << "\t.set\tmips0\n";
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MipsTargetStreamer::emitDirectiveSetMips0();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetMips1() {
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OS << "\t.set\tmips1\n";
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MipsTargetStreamer::emitDirectiveSetMips1();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetMips2() {
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OS << "\t.set\tmips2\n";
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MipsTargetStreamer::emitDirectiveSetMips2();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetMips3() {
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OS << "\t.set\tmips3\n";
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MipsTargetStreamer::emitDirectiveSetMips3();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetMips4() {
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OS << "\t.set\tmips4\n";
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MipsTargetStreamer::emitDirectiveSetMips4();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetMips5() {
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OS << "\t.set\tmips5\n";
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MipsTargetStreamer::emitDirectiveSetMips5();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetMips32() {
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OS << "\t.set\tmips32\n";
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MipsTargetStreamer::emitDirectiveSetMips32();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
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OS << "\t.set\tmips32r2\n";
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MipsTargetStreamer::emitDirectiveSetMips32R2();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetMips32R3() {
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OS << "\t.set\tmips32r3\n";
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MipsTargetStreamer::emitDirectiveSetMips32R3();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetMips32R5() {
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OS << "\t.set\tmips32r5\n";
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MipsTargetStreamer::emitDirectiveSetMips32R5();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() {
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OS << "\t.set\tmips32r6\n";
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MipsTargetStreamer::emitDirectiveSetMips32R6();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetMips64() {
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OS << "\t.set\tmips64\n";
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MipsTargetStreamer::emitDirectiveSetMips64();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
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OS << "\t.set\tmips64r2\n";
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MipsTargetStreamer::emitDirectiveSetMips64R2();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetMips64R3() {
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OS << "\t.set\tmips64r3\n";
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MipsTargetStreamer::emitDirectiveSetMips64R3();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetMips64R5() {
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OS << "\t.set\tmips64r5\n";
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MipsTargetStreamer::emitDirectiveSetMips64R5();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() {
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OS << "\t.set\tmips64r6\n";
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MipsTargetStreamer::emitDirectiveSetMips64R6();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
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OS << "\t.set\tdsp\n";
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MipsTargetStreamer::emitDirectiveSetDsp();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() {
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OS << "\t.set\tnodsp\n";
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MipsTargetStreamer::emitDirectiveSetNoDsp();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetPop() {
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OS << "\t.set\tpop\n";
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MipsTargetStreamer::emitDirectiveSetPop();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetPush() {
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OS << "\t.set\tpush\n";
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MipsTargetStreamer::emitDirectiveSetPush();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetSoftFloat() {
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OS << "\t.set\tsoftfloat\n";
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MipsTargetStreamer::emitDirectiveSetSoftFloat();
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}
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void MipsTargetAsmStreamer::emitDirectiveSetHardFloat() {
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OS << "\t.set\thardfloat\n";
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MipsTargetStreamer::emitDirectiveSetHardFloat();
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}
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// Print a 32 bit hex number with all numbers.
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static void printHex32(unsigned Value, raw_ostream &OS) {
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OS << "0x";
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for (int i = 7; i >= 0; i--)
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OS.write_hex((Value & (0xF << (i * 4))) >> (i * 4));
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}
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void MipsTargetAsmStreamer::emitMask(unsigned CPUBitmask,
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int CPUTopSavedRegOff) {
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OS << "\t.mask \t";
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printHex32(CPUBitmask, OS);
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OS << ',' << CPUTopSavedRegOff << '\n';
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}
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void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask,
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int FPUTopSavedRegOff) {
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OS << "\t.fmask\t";
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printHex32(FPUBitmask, OS);
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OS << "," << FPUTopSavedRegOff << '\n';
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}
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void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) {
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OS << "\t.cpload\t$"
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<< StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n";
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forbidModuleDirective();
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}
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void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo,
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int RegOrOffset,
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const MCSymbol &Sym,
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bool IsReg) {
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OS << "\t.cpsetup\t$"
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<< StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << ", ";
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if (IsReg)
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OS << "$"
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<< StringRef(MipsInstPrinter::getRegisterName(RegOrOffset)).lower();
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else
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OS << RegOrOffset;
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OS << ", ";
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OS << Sym.getName() << "\n";
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forbidModuleDirective();
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}
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void MipsTargetAsmStreamer::emitDirectiveModuleFP() {
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OS << "\t.module\tfp=";
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OS << ABIFlagsSection.getFpABIString(ABIFlagsSection.getFpABI()) << "\n";
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}
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void MipsTargetAsmStreamer::emitDirectiveSetFp(
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MipsABIFlagsSection::FpABIKind Value) {
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MipsTargetStreamer::emitDirectiveSetFp(Value);
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OS << "\t.set\tfp=";
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OS << ABIFlagsSection.getFpABIString(Value) << "\n";
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}
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void MipsTargetAsmStreamer::emitDirectiveModuleOddSPReg() {
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MipsTargetStreamer::emitDirectiveModuleOddSPReg();
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OS << "\t.module\t" << (ABIFlagsSection.OddSPReg ? "" : "no") << "oddspreg\n";
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}
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void MipsTargetAsmStreamer::emitDirectiveSetOddSPReg() {
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MipsTargetStreamer::emitDirectiveSetOddSPReg();
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OS << "\t.set\toddspreg\n";
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}
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void MipsTargetAsmStreamer::emitDirectiveSetNoOddSPReg() {
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MipsTargetStreamer::emitDirectiveSetNoOddSPReg();
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OS << "\t.set\tnooddspreg\n";
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}
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void MipsTargetAsmStreamer::emitDirectiveModuleSoftFloat() {
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OS << "\t.module\tsoftfloat\n";
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}
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void MipsTargetAsmStreamer::emitDirectiveModuleHardFloat() {
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OS << "\t.module\thardfloat\n";
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}
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// This part is for ELF object output.
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MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S,
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const MCSubtargetInfo &STI)
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: MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
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MCAssembler &MCA = getStreamer().getAssembler();
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Pic = MCA.getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_;
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const FeatureBitset &Features = STI.getFeatureBits();
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// Set the header flags that we can in the constructor.
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// FIXME: This is a fairly terrible hack. We set the rest
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// of these in the destructor. The problem here is two-fold:
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//
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// a: Some of the eflags can be set/reset by directives.
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// b: There aren't any usage paths that initialize the ABI
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// pointer until after we initialize either an assembler
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// or the target machine.
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// We can fix this by making the target streamer construct
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// the ABI, but this is fraught with wide ranging dependency
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// issues as well.
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unsigned EFlags = MCA.getELFHeaderEFlags();
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// Architecture
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|
if (Features[Mips::FeatureMips64r6])
|
|
EFlags |= ELF::EF_MIPS_ARCH_64R6;
|
|
else if (Features[Mips::FeatureMips64r2] ||
|
|
Features[Mips::FeatureMips64r3] ||
|
|
Features[Mips::FeatureMips64r5])
|
|
EFlags |= ELF::EF_MIPS_ARCH_64R2;
|
|
else if (Features[Mips::FeatureMips64])
|
|
EFlags |= ELF::EF_MIPS_ARCH_64;
|
|
else if (Features[Mips::FeatureMips5])
|
|
EFlags |= ELF::EF_MIPS_ARCH_5;
|
|
else if (Features[Mips::FeatureMips4])
|
|
EFlags |= ELF::EF_MIPS_ARCH_4;
|
|
else if (Features[Mips::FeatureMips3])
|
|
EFlags |= ELF::EF_MIPS_ARCH_3;
|
|
else if (Features[Mips::FeatureMips32r6])
|
|
EFlags |= ELF::EF_MIPS_ARCH_32R6;
|
|
else if (Features[Mips::FeatureMips32r2] ||
|
|
Features[Mips::FeatureMips32r3] ||
|
|
Features[Mips::FeatureMips32r5])
|
|
EFlags |= ELF::EF_MIPS_ARCH_32R2;
|
|
else if (Features[Mips::FeatureMips32])
|
|
EFlags |= ELF::EF_MIPS_ARCH_32;
|
|
else if (Features[Mips::FeatureMips2])
|
|
EFlags |= ELF::EF_MIPS_ARCH_2;
|
|
else
|
|
EFlags |= ELF::EF_MIPS_ARCH_1;
|
|
|
|
// Other options.
|
|
if (Features[Mips::FeatureNaN2008])
|
|
EFlags |= ELF::EF_MIPS_NAN2008;
|
|
|
|
// -mabicalls and -mplt are not implemented but we should act as if they were
|
|
// given.
|
|
EFlags |= ELF::EF_MIPS_CPIC;
|
|
|
|
MCA.setELFHeaderEFlags(EFlags);
|
|
}
|
|
|
|
void MipsTargetELFStreamer::emitLabel(MCSymbol *S) {
|
|
auto *Symbol = cast<MCSymbolELF>(S);
|
|
if (!isMicroMipsEnabled())
|
|
return;
|
|
getStreamer().getAssembler().registerSymbol(*Symbol);
|
|
uint8_t Type = Symbol->getType();
|
|
if (Type != ELF::STT_FUNC)
|
|
return;
|
|
|
|
Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
|
|
}
|
|
|
|
void MipsTargetELFStreamer::finish() {
|
|
MCAssembler &MCA = getStreamer().getAssembler();
|
|
const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo();
|
|
|
|
// .bss, .text and .data are always at least 16-byte aligned.
|
|
MCSection &TextSection = *OFI.getTextSection();
|
|
MCA.registerSection(TextSection);
|
|
MCSection &DataSection = *OFI.getDataSection();
|
|
MCA.registerSection(DataSection);
|
|
MCSection &BSSSection = *OFI.getBSSSection();
|
|
MCA.registerSection(BSSSection);
|
|
|
|
TextSection.setAlignment(std::max(16u, TextSection.getAlignment()));
|
|
DataSection.setAlignment(std::max(16u, DataSection.getAlignment()));
|
|
BSSSection.setAlignment(std::max(16u, BSSSection.getAlignment()));
|
|
|
|
const FeatureBitset &Features = STI.getFeatureBits();
|
|
|
|
// Update e_header flags. See the FIXME and comment above in
|
|
// the constructor for a full rundown on this.
|
|
unsigned EFlags = MCA.getELFHeaderEFlags();
|
|
|
|
// ABI
|
|
// N64 does not require any ABI bits.
|
|
if (getABI().IsO32())
|
|
EFlags |= ELF::EF_MIPS_ABI_O32;
|
|
else if (getABI().IsN32())
|
|
EFlags |= ELF::EF_MIPS_ABI2;
|
|
|
|
if (Features[Mips::FeatureGP64Bit]) {
|
|
if (getABI().IsO32())
|
|
EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */
|
|
} else if (Features[Mips::FeatureMips64r2] || Features[Mips::FeatureMips64])
|
|
EFlags |= ELF::EF_MIPS_32BITMODE;
|
|
|
|
// If we've set the cpic eflag and we're n64, go ahead and set the pic
|
|
// one as well.
|
|
if (EFlags & ELF::EF_MIPS_CPIC && getABI().IsN64())
|
|
EFlags |= ELF::EF_MIPS_PIC;
|
|
|
|
MCA.setELFHeaderEFlags(EFlags);
|
|
|
|
// Emit all the option records.
|
|
// At the moment we are only emitting .Mips.options (ODK_REGINFO) and
|
|
// .reginfo.
|
|
MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
|
|
MEF.EmitMipsOptionRecords();
|
|
|
|
emitMipsAbiFlags();
|
|
}
|
|
|
|
void MipsTargetELFStreamer::emitAssignment(MCSymbol *S, const MCExpr *Value) {
|
|
auto *Symbol = cast<MCSymbolELF>(S);
|
|
// If on rhs is micromips symbol then mark Symbol as microMips.
|
|
if (Value->getKind() != MCExpr::SymbolRef)
|
|
return;
|
|
const auto &RhsSym = cast<MCSymbolELF>(
|
|
static_cast<const MCSymbolRefExpr *>(Value)->getSymbol());
|
|
|
|
if (!(RhsSym.getOther() & ELF::STO_MIPS_MICROMIPS))
|
|
return;
|
|
|
|
Symbol->setOther(ELF::STO_MIPS_MICROMIPS);
|
|
}
|
|
|
|
MCELFStreamer &MipsTargetELFStreamer::getStreamer() {
|
|
return static_cast<MCELFStreamer &>(Streamer);
|
|
}
|
|
|
|
void MipsTargetELFStreamer::emitDirectiveSetMicroMips() {
|
|
MicroMipsEnabled = true;
|
|
|
|
MCAssembler &MCA = getStreamer().getAssembler();
|
|
unsigned Flags = MCA.getELFHeaderEFlags();
|
|
Flags |= ELF::EF_MIPS_MICROMIPS;
|
|
MCA.setELFHeaderEFlags(Flags);
|
|
forbidModuleDirective();
|
|
}
|
|
|
|
void MipsTargetELFStreamer::emitDirectiveSetNoMicroMips() {
|
|
MicroMipsEnabled = false;
|
|
forbidModuleDirective();
|
|
}
|
|
|
|
void MipsTargetELFStreamer::emitDirectiveSetMips16() {
|
|
MCAssembler &MCA = getStreamer().getAssembler();
|
|
unsigned Flags = MCA.getELFHeaderEFlags();
|
|
Flags |= ELF::EF_MIPS_ARCH_ASE_M16;
|
|
MCA.setELFHeaderEFlags(Flags);
|
|
forbidModuleDirective();
|
|
}
|
|
|
|
void MipsTargetELFStreamer::emitDirectiveSetNoReorder() {
|
|
MCAssembler &MCA = getStreamer().getAssembler();
|
|
unsigned Flags = MCA.getELFHeaderEFlags();
|
|
Flags |= ELF::EF_MIPS_NOREORDER;
|
|
MCA.setELFHeaderEFlags(Flags);
|
|
forbidModuleDirective();
|
|
}
|
|
|
|
void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) {
|
|
MCAssembler &MCA = getStreamer().getAssembler();
|
|
MCContext &Context = MCA.getContext();
|
|
MCStreamer &OS = getStreamer();
|
|
|
|
MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS,
|
|
ELF::SHF_ALLOC | ELF::SHT_REL);
|
|
|
|
const MCSymbolRefExpr *ExprRef =
|
|
MCSymbolRefExpr::create(Name, MCSymbolRefExpr::VK_None, Context);
|
|
|
|
MCA.registerSection(*Sec);
|
|
Sec->setAlignment(4);
|
|
|
|
OS.PushSection();
|
|
|
|
OS.SwitchSection(Sec);
|
|
|
|
OS.EmitValueImpl(ExprRef, 4);
|
|
|
|
OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask
|
|
OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4); // reg_offset
|
|
|
|
OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask
|
|
OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4); // fpreg_offset
|
|
|
|
OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset
|
|
OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4); // frame_reg
|
|
OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4); // return_reg
|
|
|
|
// The .end directive marks the end of a procedure. Invalidate
|
|
// the information gathered up until this point.
|
|
GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
|
|
|
|
OS.PopSection();
|
|
}
|
|
|
|
void MipsTargetELFStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {
|
|
GPRInfoSet = FPRInfoSet = FrameInfoSet = false;
|
|
}
|
|
|
|
void MipsTargetELFStreamer::emitDirectiveAbiCalls() {
|
|
MCAssembler &MCA = getStreamer().getAssembler();
|
|
unsigned Flags = MCA.getELFHeaderEFlags();
|
|
Flags |= ELF::EF_MIPS_CPIC | ELF::EF_MIPS_PIC;
|
|
MCA.setELFHeaderEFlags(Flags);
|
|
}
|
|
|
|
void MipsTargetELFStreamer::emitDirectiveNaN2008() {
|
|
MCAssembler &MCA = getStreamer().getAssembler();
|
|
unsigned Flags = MCA.getELFHeaderEFlags();
|
|
Flags |= ELF::EF_MIPS_NAN2008;
|
|
MCA.setELFHeaderEFlags(Flags);
|
|
}
|
|
|
|
void MipsTargetELFStreamer::emitDirectiveNaNLegacy() {
|
|
MCAssembler &MCA = getStreamer().getAssembler();
|
|
unsigned Flags = MCA.getELFHeaderEFlags();
|
|
Flags &= ~ELF::EF_MIPS_NAN2008;
|
|
MCA.setELFHeaderEFlags(Flags);
|
|
}
|
|
|
|
void MipsTargetELFStreamer::emitDirectiveOptionPic0() {
|
|
MCAssembler &MCA = getStreamer().getAssembler();
|
|
unsigned Flags = MCA.getELFHeaderEFlags();
|
|
// This option overrides other PIC options like -KPIC.
|
|
Pic = false;
|
|
Flags &= ~ELF::EF_MIPS_PIC;
|
|
MCA.setELFHeaderEFlags(Flags);
|
|
}
|
|
|
|
void MipsTargetELFStreamer::emitDirectiveOptionPic2() {
|
|
MCAssembler &MCA = getStreamer().getAssembler();
|
|
unsigned Flags = MCA.getELFHeaderEFlags();
|
|
Pic = true;
|
|
// NOTE: We are following the GAS behaviour here which means the directive
|
|
// 'pic2' also sets the CPIC bit in the ELF header. This is different from
|
|
// what is stated in the SYSV ABI which consider the bits EF_MIPS_PIC and
|
|
// EF_MIPS_CPIC to be mutually exclusive.
|
|
Flags |= ELF::EF_MIPS_PIC | ELF::EF_MIPS_CPIC;
|
|
MCA.setELFHeaderEFlags(Flags);
|
|
}
|
|
|
|
void MipsTargetELFStreamer::emitDirectiveInsn() {
|
|
MipsTargetStreamer::emitDirectiveInsn();
|
|
MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer);
|
|
MEF.createPendingLabelRelocs();
|
|
}
|
|
|
|
void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize,
|
|
unsigned ReturnReg_) {
|
|
MCContext &Context = getStreamer().getAssembler().getContext();
|
|
const MCRegisterInfo *RegInfo = Context.getRegisterInfo();
|
|
|
|
FrameInfoSet = true;
|
|
FrameReg = RegInfo->getEncodingValue(StackReg);
|
|
FrameOffset = StackSize;
|
|
ReturnReg = RegInfo->getEncodingValue(ReturnReg_);
|
|
}
|
|
|
|
void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask,
|
|
int CPUTopSavedRegOff) {
|
|
GPRInfoSet = true;
|
|
GPRBitMask = CPUBitmask;
|
|
GPROffset = CPUTopSavedRegOff;
|
|
}
|
|
|
|
void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask,
|
|
int FPUTopSavedRegOff) {
|
|
FPRInfoSet = true;
|
|
FPRBitMask = FPUBitmask;
|
|
FPROffset = FPUTopSavedRegOff;
|
|
}
|
|
|
|
void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) {
|
|
// .cpload $reg
|
|
// This directive expands to:
|
|
// lui $gp, %hi(_gp_disp)
|
|
// addui $gp, $gp, %lo(_gp_disp)
|
|
// addu $gp, $gp, $reg
|
|
// when support for position independent code is enabled.
|
|
if (!Pic || (getABI().IsN32() || getABI().IsN64()))
|
|
return;
|
|
|
|
// There's a GNU extension controlled by -mno-shared that allows
|
|
// locally-binding symbols to be accessed using absolute addresses.
|
|
// This is currently not supported. When supported -mno-shared makes
|
|
// .cpload expand to:
|
|
// lui $gp, %hi(__gnu_local_gp)
|
|
// addiu $gp, $gp, %lo(__gnu_local_gp)
|
|
|
|
StringRef SymName("_gp_disp");
|
|
MCAssembler &MCA = getStreamer().getAssembler();
|
|
MCSymbol *GP_Disp = MCA.getContext().getOrCreateSymbol(SymName);
|
|
MCA.registerSymbol(*GP_Disp);
|
|
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(Mips::LUi);
|
|
TmpInst.addOperand(MCOperand::createReg(Mips::GP));
|
|
const MCSymbolRefExpr *HiSym = MCSymbolRefExpr::create(
|
|
"_gp_disp", MCSymbolRefExpr::VK_Mips_ABS_HI, MCA.getContext());
|
|
TmpInst.addOperand(MCOperand::createExpr(HiSym));
|
|
getStreamer().EmitInstruction(TmpInst, STI);
|
|
|
|
TmpInst.clear();
|
|
|
|
TmpInst.setOpcode(Mips::ADDiu);
|
|
TmpInst.addOperand(MCOperand::createReg(Mips::GP));
|
|
TmpInst.addOperand(MCOperand::createReg(Mips::GP));
|
|
const MCSymbolRefExpr *LoSym = MCSymbolRefExpr::create(
|
|
"_gp_disp", MCSymbolRefExpr::VK_Mips_ABS_LO, MCA.getContext());
|
|
TmpInst.addOperand(MCOperand::createExpr(LoSym));
|
|
getStreamer().EmitInstruction(TmpInst, STI);
|
|
|
|
TmpInst.clear();
|
|
|
|
TmpInst.setOpcode(Mips::ADDu);
|
|
TmpInst.addOperand(MCOperand::createReg(Mips::GP));
|
|
TmpInst.addOperand(MCOperand::createReg(Mips::GP));
|
|
TmpInst.addOperand(MCOperand::createReg(RegNo));
|
|
getStreamer().EmitInstruction(TmpInst, STI);
|
|
|
|
forbidModuleDirective();
|
|
}
|
|
|
|
void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo,
|
|
int RegOrOffset,
|
|
const MCSymbol &Sym,
|
|
bool IsReg) {
|
|
// Only N32 and N64 emit anything for .cpsetup iff PIC is set.
|
|
if (!Pic || !(getABI().IsN32() || getABI().IsN64()))
|
|
return;
|
|
|
|
MCAssembler &MCA = getStreamer().getAssembler();
|
|
MCInst Inst;
|
|
|
|
// Either store the old $gp in a register or on the stack
|
|
if (IsReg) {
|
|
// move $save, $gpreg
|
|
Inst.setOpcode(Mips::DADDu);
|
|
Inst.addOperand(MCOperand::createReg(RegOrOffset));
|
|
Inst.addOperand(MCOperand::createReg(Mips::GP));
|
|
Inst.addOperand(MCOperand::createReg(Mips::ZERO));
|
|
} else {
|
|
// sd $gpreg, offset($sp)
|
|
Inst.setOpcode(Mips::SD);
|
|
Inst.addOperand(MCOperand::createReg(Mips::GP));
|
|
Inst.addOperand(MCOperand::createReg(Mips::SP));
|
|
Inst.addOperand(MCOperand::createImm(RegOrOffset));
|
|
}
|
|
getStreamer().EmitInstruction(Inst, STI);
|
|
Inst.clear();
|
|
|
|
const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::create(
|
|
&Sym, MCSymbolRefExpr::VK_Mips_GPOFF_HI, MCA.getContext());
|
|
const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::create(
|
|
&Sym, MCSymbolRefExpr::VK_Mips_GPOFF_LO, MCA.getContext());
|
|
|
|
// lui $gp, %hi(%neg(%gp_rel(funcSym)))
|
|
Inst.setOpcode(Mips::LUi);
|
|
Inst.addOperand(MCOperand::createReg(Mips::GP));
|
|
Inst.addOperand(MCOperand::createExpr(HiExpr));
|
|
getStreamer().EmitInstruction(Inst, STI);
|
|
Inst.clear();
|
|
|
|
// addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
|
|
Inst.setOpcode(Mips::ADDiu);
|
|
Inst.addOperand(MCOperand::createReg(Mips::GP));
|
|
Inst.addOperand(MCOperand::createReg(Mips::GP));
|
|
Inst.addOperand(MCOperand::createExpr(LoExpr));
|
|
getStreamer().EmitInstruction(Inst, STI);
|
|
Inst.clear();
|
|
|
|
// daddu $gp, $gp, $funcreg
|
|
Inst.setOpcode(Mips::DADDu);
|
|
Inst.addOperand(MCOperand::createReg(Mips::GP));
|
|
Inst.addOperand(MCOperand::createReg(Mips::GP));
|
|
Inst.addOperand(MCOperand::createReg(RegNo));
|
|
getStreamer().EmitInstruction(Inst, STI);
|
|
|
|
forbidModuleDirective();
|
|
}
|
|
|
|
void MipsTargetELFStreamer::emitMipsAbiFlags() {
|
|
MCAssembler &MCA = getStreamer().getAssembler();
|
|
MCContext &Context = MCA.getContext();
|
|
MCStreamer &OS = getStreamer();
|
|
MCSectionELF *Sec = Context.getELFSection(
|
|
".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, ELF::SHF_ALLOC, 24, "");
|
|
MCA.registerSection(*Sec);
|
|
Sec->setAlignment(8);
|
|
OS.SwitchSection(Sec);
|
|
|
|
OS << ABIFlagsSection;
|
|
}
|