mirror of
https://github.com/c64scene-ar/llvm-6502.git
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642eccbb21
All string occurences for "sparc", "Sparc" and "SPARC" were already replaced, with the exception of ELF constans in the object file descriptor as it will get removed later on (we won't be building ELF object files for the 6502).
575 lines
23 KiB
TableGen
575 lines
23 KiB
TableGen
//===-- Mos6502Instr64Bit.td - 64-bit instructions for Mos6502 Target ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains instruction definitions and patterns needed for 64-bit
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// code generation on MOS6502 v9.
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//
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// Some MOS6502 v9 instructions are defined in Mos6502InstrInfo.td because they can
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// also be used in 32-bit code running on a MOS6502 v9 CPU.
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//
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//===----------------------------------------------------------------------===//
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let Predicates = [Is64Bit] in {
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// The same integer registers are used for i32 and i64 values.
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// When registers hold i32 values, the high bits are don't care.
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// This give us free trunc and anyext.
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def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>;
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def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>;
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} // Predicates = [Is64Bit]
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//===----------------------------------------------------------------------===//
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// 64-bit Shift Instructions.
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//===----------------------------------------------------------------------===//
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//
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// The 32-bit shift instructions are still available. The left shift srl
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// instructions shift all 64 bits, but it only accepts a 5-bit shift amount.
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//
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// The srl instructions only shift the low 32 bits and clear the high 32 bits.
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// Finally, sra shifts the low 32 bits and sign-extends to 64 bits.
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let Predicates = [Is64Bit] in {
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def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>;
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def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>;
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def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>;
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def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>;
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defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, I64Regs>;
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defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, I64Regs>;
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defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, I64Regs>;
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} // Predicates = [Is64Bit]
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//===----------------------------------------------------------------------===//
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// 64-bit Immediates.
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//===----------------------------------------------------------------------===//
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//
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// All 32-bit immediates can be materialized with sethi+or, but 64-bit
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// immediates may require more code. There may be a point where it is
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// preferable to use a constant pool load instead, depending on the
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// microarchitecture.
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// Single-instruction patterns.
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// The ALU instructions want their simm13 operands as i32 immediates.
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def as_i32imm : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
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}]>;
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def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>;
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def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>;
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// Double-instruction patterns.
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// All unsigned i32 immediates can be handled by sethi+or.
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def uimm32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>;
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def : Pat<(i64 uimm32:$val), (ORri (SETHIi (HI22 $val)), (LO10 $val))>,
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Requires<[Is64Bit]>;
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// All negative i33 immediates can be handled by sethi+xor.
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def nimm33 : PatLeaf<(imm), [{
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int64_t Imm = N->getSExtValue();
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return Imm < 0 && isInt<33>(Imm);
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}]>;
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// Bits 10-31 inverted. Same as assembler's %hix.
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def HIX22 : SDNodeXForm<imm, [{
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uint64_t Val = (~N->getZExtValue() >> 10) & ((1u << 22) - 1);
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return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32);
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}]>;
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// Bits 0-9 with ones in bits 10-31. Same as assembler's %lox.
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def LOX10 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(~(~N->getZExtValue() & 0x3ff), SDLoc(N),
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MVT::i32);
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}]>;
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def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>,
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Requires<[Is64Bit]>;
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// More possible patterns:
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//
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// (sllx sethi, n)
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// (sllx simm13, n)
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//
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// 3 instrs:
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//
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// (xor (sllx sethi), simm13)
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// (sllx (xor sethi, simm13))
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//
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// 4 instrs:
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//
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// (or sethi, (sllx sethi))
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// (xnor sethi, (sllx sethi))
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//
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// 5 instrs:
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//
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// (or (sllx sethi), (or sethi, simm13))
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// (xnor (sllx sethi), (or sethi, simm13))
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// (or (sllx sethi), (sllx sethi))
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// (xnor (sllx sethi), (sllx sethi))
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//
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// Worst case is 6 instrs:
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//
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// (or (sllx (or sethi, simmm13)), (or sethi, simm13))
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// Bits 42-63, same as assembler's %hh.
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def HH22 : SDNodeXForm<imm, [{
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uint64_t Val = (N->getZExtValue() >> 42) & ((1u << 22) - 1);
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return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32);
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}]>;
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// Bits 32-41, same as assembler's %hm.
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def HM10 : SDNodeXForm<imm, [{
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uint64_t Val = (N->getZExtValue() >> 32) & ((1u << 10) - 1);
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return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32);
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}]>;
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def : Pat<(i64 imm:$val),
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(ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i32 32)),
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(ORri (SETHIi (HI22 $val)), (LO10 $val)))>,
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Requires<[Is64Bit]>;
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//===----------------------------------------------------------------------===//
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// 64-bit Integer Arithmetic and Logic.
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//===----------------------------------------------------------------------===//
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let Predicates = [Is64Bit] in {
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// Register-register instructions.
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let isCodeGenOnly = 1 in {
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defm ANDX : F3_12<"and", 0b000001, and, I64Regs, i64, i64imm>;
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defm ORX : F3_12<"or", 0b000010, or, I64Regs, i64, i64imm>;
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defm XORX : F3_12<"xor", 0b000011, xor, I64Regs, i64, i64imm>;
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def ANDXNrr : F3_1<2, 0b000101,
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(outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c),
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"andn $b, $c, $dst",
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[(set i64:$dst, (and i64:$b, (not i64:$c)))]>;
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def ORXNrr : F3_1<2, 0b000110,
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(outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c),
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"orn $b, $c, $dst",
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[(set i64:$dst, (or i64:$b, (not i64:$c)))]>;
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def XNORXrr : F3_1<2, 0b000111,
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(outs I64Regs:$dst), (ins I64Regs:$b, I64Regs:$c),
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"xnor $b, $c, $dst",
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[(set i64:$dst, (not (xor i64:$b, i64:$c)))]>;
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defm ADDX : F3_12<"add", 0b000000, add, I64Regs, i64, i64imm>;
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defm SUBX : F3_12<"sub", 0b000100, sub, I64Regs, i64, i64imm>;
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def TLS_ADDXrr : F3_1<2, 0b000000, (outs I64Regs:$rd),
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(ins I64Regs:$rs1, I64Regs:$rs2, TLSSym:$sym),
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"add $rs1, $rs2, $rd, $sym",
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[(set i64:$rd,
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(tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>;
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// "LEA" form of add
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def LEAX_ADDri : F3_2<2, 0b000000,
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(outs I64Regs:$dst), (ins MEMri:$addr),
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"add ${addr:arith}, $dst",
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[(set iPTR:$dst, ADDRri:$addr)]>;
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}
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def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>;
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def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
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def : Pat<(ctpop i64:$src), (POPCrr $src)>;
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} // Predicates = [Is64Bit]
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//===----------------------------------------------------------------------===//
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// 64-bit Integer Multiply and Divide.
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//===----------------------------------------------------------------------===//
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let Predicates = [Is64Bit] in {
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def MULXrr : F3_1<2, 0b001001,
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(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
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"mulx $rs1, $rs2, $rd",
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[(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>;
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def MULXri : F3_2<2, 0b001001,
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(outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
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"mulx $rs1, $simm13, $rd",
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[(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>;
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// Division can trap.
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let hasSideEffects = 1 in {
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def SDIVXrr : F3_1<2, 0b101101,
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(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
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"sdivx $rs1, $rs2, $rd",
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[(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>;
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def SDIVXri : F3_2<2, 0b101101,
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(outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
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"sdivx $rs1, $simm13, $rd",
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[(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$simm13)))]>;
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def UDIVXrr : F3_1<2, 0b001101,
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(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
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"udivx $rs1, $rs2, $rd",
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[(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>;
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def UDIVXri : F3_2<2, 0b001101,
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(outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
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"udivx $rs1, $simm13, $rd",
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[(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$simm13)))]>;
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} // hasSideEffects = 1
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} // Predicates = [Is64Bit]
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//===----------------------------------------------------------------------===//
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// 64-bit Loads and Stores.
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//===----------------------------------------------------------------------===//
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//
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// All the 32-bit loads and stores are available. The extending loads are sign
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// or zero-extending to 64 bits. The LDrr and LDri instructions load 32 bits
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// zero-extended to i64. Their mnemonic is lduw in MOS6502 v9 (Load Unsigned
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// Word).
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//
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// MOS6502 v9 adds 64-bit loads as well as a sign-extending ldsw i32 loads.
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let Predicates = [Is64Bit] in {
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// 64-bit loads.
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let DecoderMethod = "DecodeLoadInt" in
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defm LDX : Load<"ldx", 0b001011, load, I64Regs, i64>;
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let mayLoad = 1, isCodeGenOnly = 1, isAsmParserOnly = 1 in
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def TLS_LDXrr : F3_1<3, 0b001011,
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(outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
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"ldx [$addr], $dst, $sym",
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[(set i64:$dst,
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(tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
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// Extending loads to i64.
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def : Pat<(i64 (zextloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
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def : Pat<(i64 (zextloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
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def : Pat<(i64 (extloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
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def : Pat<(i64 (extloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
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def : Pat<(i64 (zextloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
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def : Pat<(i64 (zextloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
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def : Pat<(i64 (extloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>;
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def : Pat<(i64 (extloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>;
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def : Pat<(i64 (sextloadi8 ADDRrr:$addr)), (LDSBrr ADDRrr:$addr)>;
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def : Pat<(i64 (sextloadi8 ADDRri:$addr)), (LDSBri ADDRri:$addr)>;
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def : Pat<(i64 (zextloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>;
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def : Pat<(i64 (zextloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>;
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def : Pat<(i64 (extloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>;
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def : Pat<(i64 (extloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>;
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def : Pat<(i64 (sextloadi16 ADDRrr:$addr)), (LDSHrr ADDRrr:$addr)>;
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def : Pat<(i64 (sextloadi16 ADDRri:$addr)), (LDSHri ADDRri:$addr)>;
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def : Pat<(i64 (zextloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>;
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def : Pat<(i64 (zextloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>;
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def : Pat<(i64 (extloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>;
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def : Pat<(i64 (extloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>;
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// Sign-extending load of i32 into i64 is a new MOS6502 v9 instruction.
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let DecoderMethod = "DecodeLoadInt" in
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defm LDSW : Load<"ldsw", 0b001000, sextloadi32, I64Regs, i64>;
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// 64-bit stores.
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let DecoderMethod = "DecodeStoreInt" in
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defm STX : Store<"stx", 0b001110, store, I64Regs, i64>;
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// Truncating stores from i64 are identical to the i32 stores.
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def : Pat<(truncstorei8 i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>;
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def : Pat<(truncstorei8 i64:$src, ADDRri:$addr), (STBri ADDRri:$addr, $src)>;
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def : Pat<(truncstorei16 i64:$src, ADDRrr:$addr), (STHrr ADDRrr:$addr, $src)>;
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def : Pat<(truncstorei16 i64:$src, ADDRri:$addr), (STHri ADDRri:$addr, $src)>;
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def : Pat<(truncstorei32 i64:$src, ADDRrr:$addr), (STrr ADDRrr:$addr, $src)>;
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def : Pat<(truncstorei32 i64:$src, ADDRri:$addr), (STri ADDRri:$addr, $src)>;
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// store 0, addr -> store %g0, addr
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def : Pat<(store (i64 0), ADDRrr:$dst), (STXrr ADDRrr:$dst, (i64 G0))>;
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def : Pat<(store (i64 0), ADDRri:$dst), (STXri ADDRri:$dst, (i64 G0))>;
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} // Predicates = [Is64Bit]
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//===----------------------------------------------------------------------===//
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// 64-bit Conditionals.
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//===----------------------------------------------------------------------===//
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//
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// Flag-setting instructions like subcc and addcc set both icc and xcc flags.
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// The icc flags correspond to the 32-bit result, and the xcc are for the
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// full 64-bit result.
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//
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// We reuse CMPICC SDNodes for compares, but use new BRXCC branch nodes for
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// 64-bit compares. See LowerBR_CC.
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let Predicates = [Is64Bit] in {
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let Uses = [ICC], cc = 0b10 in
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defm BPX : IPredBranch<"%xcc", [(SPbrxcc bb:$imm19, imm:$cond)]>;
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// Conditional moves on %xcc.
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let Uses = [ICC], Constraints = "$f = $rd" in {
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let intcc = 1, cc = 0b10 in {
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def MOVXCCrr : F4_1<0b101100, (outs IntRegs:$rd),
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(ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
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"mov$cond %xcc, $rs2, $rd",
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[(set i32:$rd,
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(SPselectxcc i32:$rs2, i32:$f, imm:$cond))]>;
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def MOVXCCri : F4_2<0b101100, (outs IntRegs:$rd),
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(ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
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"mov$cond %xcc, $simm11, $rd",
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[(set i32:$rd,
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(SPselectxcc simm11:$simm11, i32:$f, imm:$cond))]>;
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} // cc
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let intcc = 1, opf_cc = 0b10 in {
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def FMOVS_XCC : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
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(ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
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"fmovs$cond %xcc, $rs2, $rd",
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[(set f32:$rd,
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(SPselectxcc f32:$rs2, f32:$f, imm:$cond))]>;
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def FMOVD_XCC : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
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(ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
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"fmovd$cond %xcc, $rs2, $rd",
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[(set f64:$rd,
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(SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>;
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def FMOVQ_XCC : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
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(ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
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"fmovq$cond %xcc, $rs2, $rd",
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[(set f128:$rd,
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(SPselectxcc f128:$rs2, f128:$f, imm:$cond))]>;
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} // opf_cc
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} // Uses, Constraints
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// Branch On integer register with Prediction (BPr).
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let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in
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multiclass BranchOnReg<bits<3> cond, string OpcStr> {
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def napt : F2_4<cond, 0, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
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!strconcat(OpcStr, " $rs1, $imm16"), []>;
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def apt : F2_4<cond, 1, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
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!strconcat(OpcStr, ",a $rs1, $imm16"), []>;
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def napn : F2_4<cond, 0, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
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!strconcat(OpcStr, ",pn $rs1, $imm16"), []>;
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def apn : F2_4<cond, 1, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16),
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!strconcat(OpcStr, ",a,pn $rs1, $imm16"), []>;
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}
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multiclass bpr_alias<string OpcStr, Instruction NAPT, Instruction APT> {
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def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"),
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(NAPT I64Regs:$rs1, bprtarget16:$imm16), 0>;
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def : InstAlias<!strconcat(OpcStr, ",a,pt $rs1, $imm16"),
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(APT I64Regs:$rs1, bprtarget16:$imm16), 0>;
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}
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|
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defm BPZ : BranchOnReg<0b001, "brz">;
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defm BPLEZ : BranchOnReg<0b010, "brlez">;
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defm BPLZ : BranchOnReg<0b011, "brlz">;
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defm BPNZ : BranchOnReg<0b101, "brnz">;
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defm BPGZ : BranchOnReg<0b110, "brgz">;
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defm BPGEZ : BranchOnReg<0b111, "brgez">;
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|
|
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defm : bpr_alias<"brz", BPZnapt, BPZapt >;
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defm : bpr_alias<"brlez", BPLEZnapt, BPLEZapt>;
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defm : bpr_alias<"brlz", BPLZnapt, BPLZapt >;
|
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defm : bpr_alias<"brnz", BPNZnapt, BPNZapt >;
|
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defm : bpr_alias<"brgz", BPGZnapt, BPGZapt >;
|
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defm : bpr_alias<"brgez", BPGEZnapt, BPGEZapt>;
|
|
|
|
// Move integer register on register condition (MOVr).
|
|
multiclass MOVR< bits<3> rcond, string OpcStr> {
|
|
def rr : F4_4r<0b101111, 0b00000, rcond, (outs I64Regs:$rd),
|
|
(ins I64Regs:$rs1, IntRegs:$rs2),
|
|
!strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
|
|
|
|
def ri : F4_4i<0b101111, rcond, (outs I64Regs:$rd),
|
|
(ins I64Regs:$rs1, i64imm:$simm10),
|
|
!strconcat(OpcStr, " $rs1, $simm10, $rd"), []>;
|
|
}
|
|
|
|
defm MOVRRZ : MOVR<0b001, "movrz">;
|
|
defm MOVRLEZ : MOVR<0b010, "movrlez">;
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|
defm MOVRLZ : MOVR<0b011, "movrlz">;
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|
defm MOVRNZ : MOVR<0b101, "movrnz">;
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|
defm MOVRGZ : MOVR<0b110, "movrgz">;
|
|
defm MOVRGEZ : MOVR<0b111, "movrgez">;
|
|
|
|
// Move FP register on integer register condition (FMOVr).
|
|
multiclass FMOVR<bits<3> rcond, string OpcStr> {
|
|
|
|
def S : F4_4r<0b110101, 0b00101, rcond,
|
|
(outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2),
|
|
!strconcat(!strconcat("fmovrs", OpcStr)," $rs1, $rs2, $rd"),
|
|
[]>;
|
|
def D : F4_4r<0b110101, 0b00110, rcond,
|
|
(outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2),
|
|
!strconcat(!strconcat("fmovrd", OpcStr)," $rs1, $rs2, $rd"),
|
|
[]>;
|
|
def Q : F4_4r<0b110101, 0b00111, rcond,
|
|
(outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2),
|
|
!strconcat(!strconcat("fmovrq", OpcStr)," $rs1, $rs2, $rd"),
|
|
[]>, Requires<[HasHardQuad]>;
|
|
}
|
|
|
|
let Predicates = [HasV9] in {
|
|
defm FMOVRZ : FMOVR<0b001, "z">;
|
|
defm FMOVRLEZ : FMOVR<0b010, "lez">;
|
|
defm FMOVRLZ : FMOVR<0b011, "lz">;
|
|
defm FMOVRNZ : FMOVR<0b101, "nz">;
|
|
defm FMOVRGZ : FMOVR<0b110, "gz">;
|
|
defm FMOVRGEZ : FMOVR<0b111, "gez">;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// 64-bit Floating Point Conversions.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
let Predicates = [Is64Bit] in {
|
|
|
|
def FXTOS : F3_3u<2, 0b110100, 0b010000100,
|
|
(outs FPRegs:$rd), (ins DFPRegs:$rs2),
|
|
"fxtos $rs2, $rd",
|
|
[(set FPRegs:$rd, (SPxtof DFPRegs:$rs2))]>;
|
|
def FXTOD : F3_3u<2, 0b110100, 0b010001000,
|
|
(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
|
|
"fxtod $rs2, $rd",
|
|
[(set DFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>;
|
|
def FXTOQ : F3_3u<2, 0b110100, 0b010001100,
|
|
(outs QFPRegs:$rd), (ins DFPRegs:$rs2),
|
|
"fxtoq $rs2, $rd",
|
|
[(set QFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>,
|
|
Requires<[HasHardQuad]>;
|
|
|
|
def FSTOX : F3_3u<2, 0b110100, 0b010000001,
|
|
(outs DFPRegs:$rd), (ins FPRegs:$rs2),
|
|
"fstox $rs2, $rd",
|
|
[(set DFPRegs:$rd, (SPftox FPRegs:$rs2))]>;
|
|
def FDTOX : F3_3u<2, 0b110100, 0b010000010,
|
|
(outs DFPRegs:$rd), (ins DFPRegs:$rs2),
|
|
"fdtox $rs2, $rd",
|
|
[(set DFPRegs:$rd, (SPftox DFPRegs:$rs2))]>;
|
|
def FQTOX : F3_3u<2, 0b110100, 0b010000011,
|
|
(outs DFPRegs:$rd), (ins QFPRegs:$rs2),
|
|
"fqtox $rs2, $rd",
|
|
[(set DFPRegs:$rd, (SPftox QFPRegs:$rs2))]>,
|
|
Requires<[HasHardQuad]>;
|
|
|
|
} // Predicates = [Is64Bit]
|
|
|
|
def : Pat<(SPselectxcc i64:$t, i64:$f, imm:$cond),
|
|
(MOVXCCrr $t, $f, imm:$cond)>;
|
|
def : Pat<(SPselectxcc (i64 simm11:$t), i64:$f, imm:$cond),
|
|
(MOVXCCri (as_i32imm $t), $f, imm:$cond)>;
|
|
|
|
def : Pat<(SPselecticc i64:$t, i64:$f, imm:$cond),
|
|
(MOVICCrr $t, $f, imm:$cond)>;
|
|
def : Pat<(SPselecticc (i64 simm11:$t), i64:$f, imm:$cond),
|
|
(MOVICCri (as_i32imm $t), $f, imm:$cond)>;
|
|
|
|
def : Pat<(SPselectfcc i64:$t, i64:$f, imm:$cond),
|
|
(MOVFCCrr $t, $f, imm:$cond)>;
|
|
def : Pat<(SPselectfcc (i64 simm11:$t), i64:$f, imm:$cond),
|
|
(MOVFCCri (as_i32imm $t), $f, imm:$cond)>;
|
|
|
|
} // Predicates = [Is64Bit]
|
|
|
|
|
|
// 64 bit SETHI
|
|
let Predicates = [Is64Bit], isCodeGenOnly = 1 in {
|
|
def SETHIXi : F2_1<0b100,
|
|
(outs IntRegs:$rd), (ins i64imm:$imm22),
|
|
"sethi $imm22, $rd",
|
|
[(set i64:$rd, SETHIimm:$imm22)]>;
|
|
}
|
|
|
|
// ATOMICS.
|
|
let Predicates = [Is64Bit], Constraints = "$swap = $rd", asi = 0b10000000 in {
|
|
def CASXrr: F3_1_asi<3, 0b111110,
|
|
(outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2,
|
|
I64Regs:$swap),
|
|
"casx [$rs1], $rs2, $rd",
|
|
[(set i64:$rd,
|
|
(atomic_cmp_swap i64:$rs1, i64:$rs2, i64:$swap))]>;
|
|
|
|
} // Predicates = [Is64Bit], Constraints = ...
|
|
|
|
let Predicates = [Is64Bit] in {
|
|
|
|
def : Pat<(atomic_fence imm, imm), (MEMBARi 0xf)>;
|
|
|
|
// atomic_load_64 addr -> load addr
|
|
def : Pat<(i64 (atomic_load ADDRrr:$src)), (LDXrr ADDRrr:$src)>;
|
|
def : Pat<(i64 (atomic_load ADDRri:$src)), (LDXri ADDRri:$src)>;
|
|
|
|
// atomic_store_64 val, addr -> store val, addr
|
|
def : Pat<(atomic_store ADDRrr:$dst, i64:$val), (STXrr ADDRrr:$dst, $val)>;
|
|
def : Pat<(atomic_store ADDRri:$dst, i64:$val), (STXri ADDRri:$dst, $val)>;
|
|
|
|
} // Predicates = [Is64Bit]
|
|
|
|
let usesCustomInserter = 1, hasCtrlDep = 1, mayLoad = 1, mayStore = 1,
|
|
Defs = [ICC] in
|
|
multiclass AtomicRMW<SDPatternOperator op32, SDPatternOperator op64> {
|
|
|
|
def _32 : Pseudo<(outs IntRegs:$rd),
|
|
(ins ptr_rc:$addr, IntRegs:$rs2), "",
|
|
[(set i32:$rd, (op32 iPTR:$addr, i32:$rs2))]>;
|
|
|
|
let Predicates = [Is64Bit] in
|
|
def _64 : Pseudo<(outs I64Regs:$rd),
|
|
(ins ptr_rc:$addr, I64Regs:$rs2), "",
|
|
[(set i64:$rd, (op64 iPTR:$addr, i64:$rs2))]>;
|
|
}
|
|
|
|
defm ATOMIC_LOAD_ADD : AtomicRMW<atomic_load_add_32, atomic_load_add_64>;
|
|
defm ATOMIC_LOAD_SUB : AtomicRMW<atomic_load_sub_32, atomic_load_sub_64>;
|
|
defm ATOMIC_LOAD_AND : AtomicRMW<atomic_load_and_32, atomic_load_and_64>;
|
|
defm ATOMIC_LOAD_OR : AtomicRMW<atomic_load_or_32, atomic_load_or_64>;
|
|
defm ATOMIC_LOAD_XOR : AtomicRMW<atomic_load_xor_32, atomic_load_xor_64>;
|
|
defm ATOMIC_LOAD_NAND : AtomicRMW<atomic_load_nand_32, atomic_load_nand_64>;
|
|
defm ATOMIC_LOAD_MIN : AtomicRMW<atomic_load_min_32, atomic_load_min_64>;
|
|
defm ATOMIC_LOAD_MAX : AtomicRMW<atomic_load_max_32, atomic_load_max_64>;
|
|
defm ATOMIC_LOAD_UMIN : AtomicRMW<atomic_load_umin_32, atomic_load_umin_64>;
|
|
defm ATOMIC_LOAD_UMAX : AtomicRMW<atomic_load_umax_32, atomic_load_umax_64>;
|
|
|
|
// There is no 64-bit variant of SWAP, so use a pseudo.
|
|
let usesCustomInserter = 1, hasCtrlDep = 1, mayLoad = 1, mayStore = 1,
|
|
Defs = [ICC], Predicates = [Is64Bit] in
|
|
def ATOMIC_SWAP_64 : Pseudo<(outs I64Regs:$rd),
|
|
(ins ptr_rc:$addr, I64Regs:$rs2), "",
|
|
[(set i64:$rd,
|
|
(atomic_swap_64 iPTR:$addr, i64:$rs2))]>;
|
|
|
|
let Predicates = [Is64Bit], hasSideEffects = 1, Uses = [ICC], cc = 0b10 in
|
|
defm TXCC : TRAP<"%xcc">;
|
|
|
|
// Global addresses, constant pool entries
|
|
let Predicates = [Is64Bit] in {
|
|
|
|
def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
|
|
def : Pat<(SPlo tglobaladdr:$in), (ORXri (i64 G0), tglobaladdr:$in)>;
|
|
def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
|
|
def : Pat<(SPlo tconstpool:$in), (ORXri (i64 G0), tconstpool:$in)>;
|
|
|
|
// GlobalTLS addresses
|
|
def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
|
|
def : Pat<(SPlo tglobaltlsaddr:$in), (ORXri (i64 G0), tglobaltlsaddr:$in)>;
|
|
def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
|
|
(ADDXri (SETHIXi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
|
|
def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
|
|
(XORXri (SETHIXi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
|
|
|
|
// Blockaddress
|
|
def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
|
|
def : Pat<(SPlo tblockaddress:$in), (ORXri (i64 G0), tblockaddress:$in)>;
|
|
|
|
// Add reg, lo. This is used when taking the addr of a global/constpool entry.
|
|
def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDXri $r, tglobaladdr:$in)>;
|
|
def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDXri $r, tconstpool:$in)>;
|
|
def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
|
|
(ADDXri $r, tblockaddress:$in)>;
|
|
}
|