mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49809 91177308-0d34-0410-b5e6-96231b3b80d8
940 lines
32 KiB
C++
940 lines
32 KiB
C++
//===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMInstrInfo.h"
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#include "ARM.h"
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#include "ARMAddressingModes.h"
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#include "ARMGenInstrInfo.inc"
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#include "ARMMachineFunctionInfo.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/Target/TargetAsmInfo.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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static cl::opt<bool> EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
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cl::desc("Enable ARM 2-addr to 3-addr conv"));
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static inline
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const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
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return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
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}
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static inline
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const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
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return MIB.addReg(0);
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}
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ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
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: TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
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RI(*this, STI) {
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}
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const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
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return &ARM::GPRRegClass;
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}
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/// Return true if the instruction is a register to register move and
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/// leave the source and dest operands in the passed parameters.
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///
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bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg) const {
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unsigned oc = MI.getOpcode();
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switch (oc) {
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default:
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return false;
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case ARM::FCPYS:
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case ARM::FCPYD:
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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return true;
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case ARM::MOVr:
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case ARM::tMOVr:
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assert(MI.getDesc().getNumOperands() >= 2 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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"Invalid ARM MOV instruction");
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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return true;
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}
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}
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unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
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switch (MI->getOpcode()) {
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default: break;
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case ARM::LDR:
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if (MI->getOperand(1).isFrameIndex() &&
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MI->getOperand(2).isRegister() &&
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MI->getOperand(3).isImmediate() &&
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MI->getOperand(2).getReg() == 0 &&
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MI->getOperand(3).getImm() == 0) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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case ARM::FLDD:
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case ARM::FLDS:
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if (MI->getOperand(1).isFrameIndex() &&
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MI->getOperand(2).isImmediate() &&
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MI->getOperand(2).getImm() == 0) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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case ARM::tRestore:
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if (MI->getOperand(1).isFrameIndex() &&
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MI->getOperand(2).isImmediate() &&
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MI->getOperand(2).getImm() == 0) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case ARM::STR:
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if (MI->getOperand(1).isFrameIndex() &&
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MI->getOperand(2).isRegister() &&
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MI->getOperand(3).isImmediate() &&
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MI->getOperand(2).getReg() == 0 &&
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MI->getOperand(3).getImm() == 0) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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case ARM::FSTD:
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case ARM::FSTS:
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if (MI->getOperand(1).isFrameIndex() &&
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MI->getOperand(2).isImmediate() &&
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MI->getOperand(2).getImm() == 0) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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case ARM::tSpill:
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if (MI->getOperand(1).isFrameIndex() &&
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MI->getOperand(2).isImmediate() &&
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MI->getOperand(2).getImm() == 0) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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void ARMInstrInfo::reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg,
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const MachineInstr *Orig) const {
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if (Orig->getOpcode() == ARM::MOVi2pieces) {
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RI.emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImm(),
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Orig->getOperand(2).getImm(),
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Orig->getOperand(3).getReg(), this, false);
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return;
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}
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MachineInstr *MI = Orig->clone();
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MI->getOperand(0).setReg(DestReg);
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MBB.insert(I, MI);
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}
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static unsigned getUnindexedOpcode(unsigned Opc) {
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switch (Opc) {
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default: break;
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case ARM::LDR_PRE:
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case ARM::LDR_POST:
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return ARM::LDR;
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case ARM::LDRH_PRE:
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case ARM::LDRH_POST:
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return ARM::LDRH;
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case ARM::LDRB_PRE:
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case ARM::LDRB_POST:
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return ARM::LDRB;
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case ARM::LDRSH_PRE:
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case ARM::LDRSH_POST:
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return ARM::LDRSH;
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case ARM::LDRSB_PRE:
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case ARM::LDRSB_POST:
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return ARM::LDRSB;
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case ARM::STR_PRE:
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case ARM::STR_POST:
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return ARM::STR;
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case ARM::STRH_PRE:
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case ARM::STRH_POST:
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return ARM::STRH;
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case ARM::STRB_PRE:
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case ARM::STRB_POST:
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return ARM::STRB;
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}
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return 0;
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}
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MachineInstr *
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ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI,
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LiveVariables &LV) const {
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if (!EnableARM3Addr)
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return NULL;
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MachineInstr *MI = MBBI;
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unsigned TSFlags = MI->getDesc().TSFlags;
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bool isPre = false;
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switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
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default: return NULL;
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case ARMII::IndexModePre:
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isPre = true;
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break;
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case ARMII::IndexModePost:
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break;
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}
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// Try spliting an indexed load / store to a un-indexed one plus an add/sub
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// operation.
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unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
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if (MemOpc == 0)
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return NULL;
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MachineInstr *UpdateMI = NULL;
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MachineInstr *MemMI = NULL;
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unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
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const TargetInstrDesc &TID = MI->getDesc();
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unsigned NumOps = TID.getNumOperands();
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bool isLoad = !TID.mayStore();
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const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
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const MachineOperand &Base = MI->getOperand(2);
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const MachineOperand &Offset = MI->getOperand(NumOps-3);
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unsigned WBReg = WB.getReg();
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unsigned BaseReg = Base.getReg();
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unsigned OffReg = Offset.getReg();
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unsigned OffImm = MI->getOperand(NumOps-2).getImm();
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ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
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switch (AddrMode) {
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default:
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assert(false && "Unknown indexed op!");
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return NULL;
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case ARMII::AddrMode2: {
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bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
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unsigned Amt = ARM_AM::getAM2Offset(OffImm);
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if (OffReg == 0) {
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int SOImmVal = ARM_AM::getSOImmVal(Amt);
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if (SOImmVal == -1)
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// Can't encode it in a so_imm operand. This transformation will
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// add more than 1 instruction. Abandon!
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return NULL;
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UpdateMI = BuildMI(get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
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.addReg(BaseReg).addImm(SOImmVal)
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.addImm(Pred).addReg(0).addReg(0);
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} else if (Amt != 0) {
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ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
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unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
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UpdateMI = BuildMI(get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
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.addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
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.addImm(Pred).addReg(0).addReg(0);
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} else
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UpdateMI = BuildMI(get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
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.addReg(BaseReg).addReg(OffReg)
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.addImm(Pred).addReg(0).addReg(0);
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break;
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}
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case ARMII::AddrMode3 : {
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bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
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unsigned Amt = ARM_AM::getAM3Offset(OffImm);
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if (OffReg == 0)
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// Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
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UpdateMI = BuildMI(get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
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.addReg(BaseReg).addImm(Amt)
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.addImm(Pred).addReg(0).addReg(0);
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else
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UpdateMI = BuildMI(get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
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.addReg(BaseReg).addReg(OffReg)
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.addImm(Pred).addReg(0).addReg(0);
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break;
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}
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}
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std::vector<MachineInstr*> NewMIs;
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if (isPre) {
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if (isLoad)
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MemMI = BuildMI(get(MemOpc), MI->getOperand(0).getReg())
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.addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
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else
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MemMI = BuildMI(get(MemOpc)).addReg(MI->getOperand(1).getReg())
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.addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
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NewMIs.push_back(MemMI);
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NewMIs.push_back(UpdateMI);
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} else {
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if (isLoad)
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MemMI = BuildMI(get(MemOpc), MI->getOperand(0).getReg())
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.addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
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else
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MemMI = BuildMI(get(MemOpc)).addReg(MI->getOperand(1).getReg())
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.addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
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if (WB.isDead())
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UpdateMI->getOperand(0).setIsDead();
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NewMIs.push_back(UpdateMI);
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NewMIs.push_back(MemMI);
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}
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// Transfer LiveVariables states, kill / dead info.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegister() && MO.getReg() &&
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TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
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unsigned Reg = MO.getReg();
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LiveVariables::VarInfo &VI = LV.getVarInfo(Reg);
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if (MO.isDef()) {
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MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
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if (MO.isDead())
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LV.addVirtualRegisterDead(Reg, NewMI);
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}
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if (MO.isUse() && MO.isKill()) {
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for (unsigned j = 0; j < 2; ++j) {
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// Look at the two new MI's in reverse order.
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MachineInstr *NewMI = NewMIs[j];
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if (!NewMI->readsRegister(Reg))
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continue;
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LV.addVirtualRegisterKilled(Reg, NewMI);
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if (VI.removeKill(MI))
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VI.Kills.push_back(NewMI);
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break;
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}
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}
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}
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}
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MFI->insert(MBBI, NewMIs[1]);
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MFI->insert(MBBI, NewMIs[0]);
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return NewMIs[0];
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}
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// Branch analysis.
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bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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std::vector<MachineOperand> &Cond) const {
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
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return false;
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// Get the last instruction in the block.
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MachineInstr *LastInst = I;
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// If there is only one terminator instruction, process it.
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unsigned LastOpc = LastInst->getOpcode();
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
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if (LastOpc == ARM::B || LastOpc == ARM::tB) {
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
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// Block ends with fall-through condbranch.
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TBB = LastInst->getOperand(0).getMBB();
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Cond.push_back(LastInst->getOperand(1));
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Cond.push_back(LastInst->getOperand(2));
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return false;
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}
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return true; // Can't handle indirect branch.
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}
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// Get the instruction before it if it is a terminator.
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MachineInstr *SecondLastInst = I;
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// If there are three terminators, we don't know what sort of block this is.
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if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
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return true;
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// If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it.
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unsigned SecondLastOpc = SecondLastInst->getOpcode();
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if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
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(SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
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TBB = SecondLastInst->getOperand(0).getMBB();
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Cond.push_back(SecondLastInst->getOperand(1));
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Cond.push_back(SecondLastInst->getOperand(2));
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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// If the block ends with two unconditional branches, handle it. The second
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// one is not executed, so remove it.
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if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &&
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(LastOpc == ARM::B || LastOpc == ARM::tB)) {
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TBB = SecondLastInst->getOperand(0).getMBB();
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I = LastInst;
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I->eraseFromParent();
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return false;
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}
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// Likewise if it ends with a branch table followed by an unconditional branch.
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// The branch folder can create these, and we must get rid of them for
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// correctness of Thumb constant islands.
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if ((SecondLastOpc == ARM::BR_JTr || SecondLastOpc==ARM::BR_JTm ||
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SecondLastOpc == ARM::BR_JTadd || SecondLastOpc==ARM::tBR_JTr) &&
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(LastOpc == ARM::B || LastOpc == ARM::tB)) {
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I = LastInst;
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I->eraseFromParent();
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return true;
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}
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// Otherwise, can't handle this.
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return true;
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}
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unsigned ARMInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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MachineFunction &MF = *MBB.getParent();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
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int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin()) return 0;
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--I;
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if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc)
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return 0;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
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if (I == MBB.begin()) return 1;
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--I;
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if (I->getOpcode() != BccOpc)
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return 1;
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// Remove the branch.
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I->eraseFromParent();
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return 2;
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}
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unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const std::vector<MachineOperand> &Cond) const {
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MachineFunction &MF = *MBB.getParent();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
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int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 2 || Cond.size() == 0) &&
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"ARM branch conditions have two components!");
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if (FBB == 0) {
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if (Cond.empty()) // Unconditional branch?
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BuildMI(&MBB, get(BOpc)).addMBB(TBB);
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else
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BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
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return 1;
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}
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// Two-way conditional branch.
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BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
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.addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
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BuildMI(&MBB, get(BOpc)).addMBB(FBB);
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return 2;
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}
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void ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
|
|
const TargetRegisterClass *SrcRC) const {
|
|
if (DestRC != SrcRC) {
|
|
cerr << "Not yet supported!";
|
|
abort();
|
|
}
|
|
|
|
if (DestRC == ARM::GPRRegisterClass) {
|
|
MachineFunction &MF = *MBB.getParent();
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
if (AFI->isThumbFunction())
|
|
BuildMI(MBB, I, get(ARM::tMOVr), DestReg).addReg(SrcReg);
|
|
else
|
|
AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, get(ARM::MOVr), DestReg)
|
|
.addReg(SrcReg)));
|
|
} else if (DestRC == ARM::SPRRegisterClass)
|
|
AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYS), DestReg)
|
|
.addReg(SrcReg));
|
|
else if (DestRC == ARM::DPRRegisterClass)
|
|
AddDefaultPred(BuildMI(MBB, I, get(ARM::FCPYD), DestReg)
|
|
.addReg(SrcReg));
|
|
else
|
|
abort();
|
|
}
|
|
|
|
static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB,
|
|
MachineOperand &MO) {
|
|
if (MO.isRegister())
|
|
MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
|
|
else if (MO.isImmediate())
|
|
MIB = MIB.addImm(MO.getImm());
|
|
else if (MO.isFrameIndex())
|
|
MIB = MIB.addFrameIndex(MO.getIndex());
|
|
else
|
|
assert(0 && "Unknown operand for ARMInstrAddOperand!");
|
|
|
|
return MIB;
|
|
}
|
|
|
|
void ARMInstrInfo::
|
|
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
unsigned SrcReg, bool isKill, int FI,
|
|
const TargetRegisterClass *RC) const {
|
|
if (RC == ARM::GPRRegisterClass) {
|
|
MachineFunction &MF = *MBB.getParent();
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
if (AFI->isThumbFunction())
|
|
BuildMI(MBB, I, get(ARM::tSpill)).addReg(SrcReg, false, false, isKill)
|
|
.addFrameIndex(FI).addImm(0);
|
|
else
|
|
AddDefaultPred(BuildMI(MBB, I, get(ARM::STR))
|
|
.addReg(SrcReg, false, false, isKill)
|
|
.addFrameIndex(FI).addReg(0).addImm(0));
|
|
} else if (RC == ARM::DPRRegisterClass) {
|
|
AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTD))
|
|
.addReg(SrcReg, false, false, isKill)
|
|
.addFrameIndex(FI).addImm(0));
|
|
} else {
|
|
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
|
|
AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTS))
|
|
.addReg(SrcReg, false, false, isKill)
|
|
.addFrameIndex(FI).addImm(0));
|
|
}
|
|
}
|
|
|
|
void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
|
bool isKill,
|
|
SmallVectorImpl<MachineOperand> &Addr,
|
|
const TargetRegisterClass *RC,
|
|
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
|
unsigned Opc = 0;
|
|
if (RC == ARM::GPRRegisterClass) {
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
if (AFI->isThumbFunction()) {
|
|
Opc = Addr[0].isFrameIndex() ? ARM::tSpill : ARM::tSTR;
|
|
MachineInstrBuilder MIB =
|
|
BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill);
|
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
|
MIB = ARMInstrAddOperand(MIB, Addr[i]);
|
|
NewMIs.push_back(MIB);
|
|
return;
|
|
}
|
|
Opc = ARM::STR;
|
|
} else if (RC == ARM::DPRRegisterClass) {
|
|
Opc = ARM::FSTD;
|
|
} else {
|
|
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
|
|
Opc = ARM::FSTS;
|
|
}
|
|
|
|
MachineInstrBuilder MIB =
|
|
BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill);
|
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
|
MIB = ARMInstrAddOperand(MIB, Addr[i]);
|
|
AddDefaultPred(MIB);
|
|
NewMIs.push_back(MIB);
|
|
return;
|
|
}
|
|
|
|
void ARMInstrInfo::
|
|
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
unsigned DestReg, int FI,
|
|
const TargetRegisterClass *RC) const {
|
|
if (RC == ARM::GPRRegisterClass) {
|
|
MachineFunction &MF = *MBB.getParent();
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
if (AFI->isThumbFunction())
|
|
BuildMI(MBB, I, get(ARM::tRestore), DestReg)
|
|
.addFrameIndex(FI).addImm(0);
|
|
else
|
|
AddDefaultPred(BuildMI(MBB, I, get(ARM::LDR), DestReg)
|
|
.addFrameIndex(FI).addReg(0).addImm(0));
|
|
} else if (RC == ARM::DPRRegisterClass) {
|
|
AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDD), DestReg)
|
|
.addFrameIndex(FI).addImm(0));
|
|
} else {
|
|
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
|
|
AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDS), DestReg)
|
|
.addFrameIndex(FI).addImm(0));
|
|
}
|
|
}
|
|
|
|
void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
SmallVectorImpl<MachineOperand> &Addr,
|
|
const TargetRegisterClass *RC,
|
|
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
|
unsigned Opc = 0;
|
|
if (RC == ARM::GPRRegisterClass) {
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
if (AFI->isThumbFunction()) {
|
|
Opc = Addr[0].isFrameIndex() ? ARM::tRestore : ARM::tLDR;
|
|
MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
|
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
|
MIB = ARMInstrAddOperand(MIB, Addr[i]);
|
|
NewMIs.push_back(MIB);
|
|
return;
|
|
}
|
|
Opc = ARM::LDR;
|
|
} else if (RC == ARM::DPRRegisterClass) {
|
|
Opc = ARM::FLDD;
|
|
} else {
|
|
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
|
|
Opc = ARM::FLDS;
|
|
}
|
|
|
|
MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
|
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
|
MIB = ARMInstrAddOperand(MIB, Addr[i]);
|
|
AddDefaultPred(MIB);
|
|
NewMIs.push_back(MIB);
|
|
return;
|
|
}
|
|
|
|
bool ARMInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
const std::vector<CalleeSavedInfo> &CSI) const {
|
|
MachineFunction &MF = *MBB.getParent();
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
if (!AFI->isThumbFunction() || CSI.empty())
|
|
return false;
|
|
|
|
MachineInstrBuilder MIB = BuildMI(MBB, MI, get(ARM::tPUSH));
|
|
for (unsigned i = CSI.size(); i != 0; --i) {
|
|
unsigned Reg = CSI[i-1].getReg();
|
|
// Add the callee-saved register as live-in. It's killed at the spill.
|
|
MBB.addLiveIn(Reg);
|
|
MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool ARMInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI,
|
|
const std::vector<CalleeSavedInfo> &CSI) const {
|
|
MachineFunction &MF = *MBB.getParent();
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
if (!AFI->isThumbFunction() || CSI.empty())
|
|
return false;
|
|
|
|
bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
|
|
MachineInstr *PopMI = new MachineInstr(get(ARM::tPOP));
|
|
MBB.insert(MI, PopMI);
|
|
for (unsigned i = CSI.size(); i != 0; --i) {
|
|
unsigned Reg = CSI[i-1].getReg();
|
|
if (Reg == ARM::LR) {
|
|
// Special epilogue for vararg functions. See emitEpilogue
|
|
if (isVarArg)
|
|
continue;
|
|
Reg = ARM::PC;
|
|
PopMI->setDesc(get(ARM::tPOP_RET));
|
|
MBB.erase(MI);
|
|
}
|
|
PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
|
|
}
|
|
return true;
|
|
}
|
|
|
|
MachineInstr *ARMInstrInfo::foldMemoryOperand(MachineFunction &MF,
|
|
MachineInstr *MI,
|
|
SmallVectorImpl<unsigned> &Ops,
|
|
int FI) const {
|
|
if (Ops.size() != 1) return NULL;
|
|
|
|
unsigned OpNum = Ops[0];
|
|
unsigned Opc = MI->getOpcode();
|
|
MachineInstr *NewMI = NULL;
|
|
switch (Opc) {
|
|
default: break;
|
|
case ARM::MOVr: {
|
|
if (MI->getOperand(4).getReg() == ARM::CPSR)
|
|
// If it is updating CPSR, then it cannot be foled.
|
|
break;
|
|
unsigned Pred = MI->getOperand(2).getImm();
|
|
unsigned PredReg = MI->getOperand(3).getReg();
|
|
if (OpNum == 0) { // move -> store
|
|
unsigned SrcReg = MI->getOperand(1).getReg();
|
|
NewMI = BuildMI(get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI)
|
|
.addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
|
|
} else { // move -> load
|
|
unsigned DstReg = MI->getOperand(0).getReg();
|
|
NewMI = BuildMI(get(ARM::LDR), DstReg).addFrameIndex(FI).addReg(0)
|
|
.addImm(0).addImm(Pred).addReg(PredReg);
|
|
}
|
|
break;
|
|
}
|
|
case ARM::tMOVr: {
|
|
if (OpNum == 0) { // move -> store
|
|
unsigned SrcReg = MI->getOperand(1).getReg();
|
|
if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
|
|
// tSpill cannot take a high register operand.
|
|
break;
|
|
NewMI = BuildMI(get(ARM::tSpill)).addReg(SrcReg).addFrameIndex(FI)
|
|
.addImm(0);
|
|
} else { // move -> load
|
|
unsigned DstReg = MI->getOperand(0).getReg();
|
|
if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
|
|
// tRestore cannot target a high register operand.
|
|
break;
|
|
NewMI = BuildMI(get(ARM::tRestore), DstReg).addFrameIndex(FI)
|
|
.addImm(0);
|
|
}
|
|
break;
|
|
}
|
|
case ARM::FCPYS: {
|
|
unsigned Pred = MI->getOperand(2).getImm();
|
|
unsigned PredReg = MI->getOperand(3).getReg();
|
|
if (OpNum == 0) { // move -> store
|
|
unsigned SrcReg = MI->getOperand(1).getReg();
|
|
NewMI = BuildMI(get(ARM::FSTS)).addReg(SrcReg).addFrameIndex(FI)
|
|
.addImm(0).addImm(Pred).addReg(PredReg);
|
|
} else { // move -> load
|
|
unsigned DstReg = MI->getOperand(0).getReg();
|
|
NewMI = BuildMI(get(ARM::FLDS), DstReg).addFrameIndex(FI)
|
|
.addImm(0).addImm(Pred).addReg(PredReg);
|
|
}
|
|
break;
|
|
}
|
|
case ARM::FCPYD: {
|
|
unsigned Pred = MI->getOperand(2).getImm();
|
|
unsigned PredReg = MI->getOperand(3).getReg();
|
|
if (OpNum == 0) { // move -> store
|
|
unsigned SrcReg = MI->getOperand(1).getReg();
|
|
NewMI = BuildMI(get(ARM::FSTD)).addReg(SrcReg).addFrameIndex(FI)
|
|
.addImm(0).addImm(Pred).addReg(PredReg);
|
|
} else { // move -> load
|
|
unsigned DstReg = MI->getOperand(0).getReg();
|
|
NewMI = BuildMI(get(ARM::FLDD), DstReg).addFrameIndex(FI)
|
|
.addImm(0).addImm(Pred).addReg(PredReg);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (NewMI)
|
|
NewMI->copyKillDeadInfo(MI);
|
|
return NewMI;
|
|
}
|
|
|
|
bool ARMInstrInfo::canFoldMemoryOperand(MachineInstr *MI,
|
|
SmallVectorImpl<unsigned> &Ops) const {
|
|
if (Ops.size() != 1) return false;
|
|
|
|
unsigned OpNum = Ops[0];
|
|
unsigned Opc = MI->getOpcode();
|
|
switch (Opc) {
|
|
default: break;
|
|
case ARM::MOVr:
|
|
// If it is updating CPSR, then it cannot be foled.
|
|
return MI->getOperand(4).getReg() != ARM::CPSR;
|
|
case ARM::tMOVr: {
|
|
if (OpNum == 0) { // move -> store
|
|
unsigned SrcReg = MI->getOperand(1).getReg();
|
|
if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
|
|
// tSpill cannot take a high register operand.
|
|
return false;
|
|
} else { // move -> load
|
|
unsigned DstReg = MI->getOperand(0).getReg();
|
|
if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
|
|
// tRestore cannot target a high register operand.
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
case ARM::FCPYS:
|
|
case ARM::FCPYD:
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
bool ARMInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
|
|
if (MBB.empty()) return false;
|
|
|
|
switch (MBB.back().getOpcode()) {
|
|
case ARM::BX_RET: // Return.
|
|
case ARM::LDM_RET:
|
|
case ARM::tBX_RET:
|
|
case ARM::tBX_RET_vararg:
|
|
case ARM::tPOP_RET:
|
|
case ARM::B:
|
|
case ARM::tB: // Uncond branch.
|
|
case ARM::tBR_JTr:
|
|
case ARM::BR_JTr: // Jumptable branch.
|
|
case ARM::BR_JTm: // Jumptable branch through mem.
|
|
case ARM::BR_JTadd: // Jumptable branch add to pc.
|
|
return true;
|
|
default: return false;
|
|
}
|
|
}
|
|
|
|
bool ARMInstrInfo::
|
|
ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
|
|
ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
|
|
Cond[0].setImm(ARMCC::getOppositeCondition(CC));
|
|
return false;
|
|
}
|
|
|
|
bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
|
|
int PIdx = MI->findFirstPredOperandIdx();
|
|
return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
|
|
}
|
|
|
|
bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
|
|
const std::vector<MachineOperand> &Pred) const {
|
|
unsigned Opc = MI->getOpcode();
|
|
if (Opc == ARM::B || Opc == ARM::tB) {
|
|
MI->setDesc(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
|
|
MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
|
|
MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
|
|
return true;
|
|
}
|
|
|
|
int PIdx = MI->findFirstPredOperandIdx();
|
|
if (PIdx != -1) {
|
|
MachineOperand &PMO = MI->getOperand(PIdx);
|
|
PMO.setImm(Pred[0].getImm());
|
|
MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool
|
|
ARMInstrInfo::SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
|
|
const std::vector<MachineOperand> &Pred2) const{
|
|
if (Pred1.size() > 2 || Pred2.size() > 2)
|
|
return false;
|
|
|
|
ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
|
|
ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
|
|
if (CC1 == CC2)
|
|
return true;
|
|
|
|
switch (CC1) {
|
|
default:
|
|
return false;
|
|
case ARMCC::AL:
|
|
return true;
|
|
case ARMCC::HS:
|
|
return CC2 == ARMCC::HI;
|
|
case ARMCC::LS:
|
|
return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
|
|
case ARMCC::GE:
|
|
return CC2 == ARMCC::GT;
|
|
case ARMCC::LE:
|
|
return CC2 == ARMCC::LT;
|
|
}
|
|
}
|
|
|
|
bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
|
|
std::vector<MachineOperand> &Pred) const {
|
|
const TargetInstrDesc &TID = MI->getDesc();
|
|
if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
|
|
return false;
|
|
|
|
bool Found = false;
|
|
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
|
const MachineOperand &MO = MI->getOperand(i);
|
|
if (MO.isRegister() && MO.getReg() == ARM::CPSR) {
|
|
Pred.push_back(MO);
|
|
Found = true;
|
|
}
|
|
}
|
|
|
|
return Found;
|
|
}
|
|
|
|
|
|
/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
|
|
static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
|
|
unsigned JTI) DISABLE_INLINE;
|
|
static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
|
|
unsigned JTI) {
|
|
return JT[JTI].MBBs.size();
|
|
}
|
|
|
|
/// GetInstSize - Return the size of the specified MachineInstr.
|
|
///
|
|
unsigned ARMInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
|
|
const MachineBasicBlock &MBB = *MI->getParent();
|
|
const MachineFunction *MF = MBB.getParent();
|
|
const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
|
|
|
|
// Basic size info comes from the TSFlags field.
|
|
const TargetInstrDesc &TID = MI->getDesc();
|
|
unsigned TSFlags = TID.TSFlags;
|
|
|
|
switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
|
|
default:
|
|
// If this machine instr is an inline asm, measure it.
|
|
if (MI->getOpcode() == ARM::INLINEASM)
|
|
return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
|
|
if (MI->getOpcode() == ARM::LABEL)
|
|
return 0;
|
|
if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
|
|
return 0;
|
|
assert(0 && "Unknown or unset size field for instr!");
|
|
break;
|
|
case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
|
|
case ARMII::Size4Bytes: return 4; // Arm instruction.
|
|
case ARMII::Size2Bytes: return 2; // Thumb instruction.
|
|
case ARMII::SizeSpecial: {
|
|
switch (MI->getOpcode()) {
|
|
case ARM::CONSTPOOL_ENTRY:
|
|
// If this machine instr is a constant pool entry, its size is recorded as
|
|
// operand #2.
|
|
return MI->getOperand(2).getImm();
|
|
case ARM::BR_JTr:
|
|
case ARM::BR_JTm:
|
|
case ARM::BR_JTadd:
|
|
case ARM::tBR_JTr: {
|
|
// These are jumptable branches, i.e. a branch followed by an inlined
|
|
// jumptable. The size is 4 + 4 * number of entries.
|
|
unsigned NumOps = TID.getNumOperands();
|
|
MachineOperand JTOP =
|
|
MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
|
|
unsigned JTI = JTOP.getIndex();
|
|
MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
|
|
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
|
|
assert(JTI < JT.size());
|
|
// Thumb instructions are 2 byte aligned, but JT entries are 4 byte
|
|
// 4 aligned. The assembler / linker may add 2 byte padding just before
|
|
// the JT entries. The size does not include this padding; the
|
|
// constant islands pass does separate bookkeeping for it.
|
|
// FIXME: If we know the size of the function is less than (1 << 16) *2
|
|
// bytes, we can use 16-bit entries instead. Then there won't be an
|
|
// alignment issue.
|
|
return getNumJTEntries(JT, JTI) * 4 +
|
|
(MI->getOpcode()==ARM::tBR_JTr ? 2 : 4);
|
|
}
|
|
default:
|
|
// Otherwise, pseudo-instruction sizes are zero.
|
|
return 0;
|
|
}
|
|
}
|
|
}
|
|
return 0; // Not reached
|
|
}
|