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https://github.com/c64scene-ar/llvm-6502.git
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7f0125ba19
they can be better handled and optimized in the Mips16 constant island code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192520 91177308-0d34-0410-b5e6-96231b3b80d8
1851 lines
49 KiB
TableGen
1851 lines
49 KiB
TableGen
//===- Mips16InstrInfo.td - Target Description for Mips16 -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips16 instructions.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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// Mips Address
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//
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def addr16 :
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ComplexPattern<iPTR, 3, "selectAddr16", [frameindex], [SDNPWantParent]>;
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//
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// Address operand
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def mem16 : Operand<i32> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops CPU16Regs, simm16, CPU16RegsPlusSP);
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let EncoderMethod = "getMemEncoding";
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}
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def mem16_ea : Operand<i32> {
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let PrintMethod = "printMemOperandEA";
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let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
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let EncoderMethod = "getMemEncoding";
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}
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//
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//
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// I8 instruction format
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//
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class FI816_ins_base<bits<3> _func, string asmstr,
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string asmstr2, InstrItinClass itin>:
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FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
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[], itin>;
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class FI816_SP_ins<bits<3> _func, string asmstr,
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InstrItinClass itin>:
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FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>;
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//
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// RI instruction format
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//
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class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
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InstrItinClass itin>:
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FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
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!strconcat(asmstr, asmstr2), [], itin>;
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class FRI16_ins<bits<5> op, string asmstr,
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InstrItinClass itin>:
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FRI16_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
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class FRI16R_ins_base<bits<5> op, string asmstr, string asmstr2,
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InstrItinClass itin>:
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FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
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!strconcat(asmstr, asmstr2), [], itin>;
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class FRI16R_ins<bits<5> op, string asmstr,
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InstrItinClass itin>:
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FRI16R_ins_base<op, asmstr, "\t$rx, $imm \t# 16 bit inst", itin>;
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class F2RI16_ins<bits<5> _op, string asmstr,
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InstrItinClass itin>:
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FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
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!strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> {
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let Constraints = "$rx_ = $rx";
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}
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class FRI16_B_ins<bits<5> _op, string asmstr,
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InstrItinClass itin>:
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FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
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!strconcat(asmstr, "\t$rx, $imm # 16 bit inst"), [], itin>;
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//
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// Compare a register and immediate and place result in CC
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// Implicit use of T8
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//
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// EXT-CCRR Instruction format
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//
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class FEXT_CCRXI16_ins<string asmstr>:
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MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
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!strconcat(asmstr, "\t$rx, $imm\n\tmove\t$cc, $$t8"), []> {
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let isCodeGenOnly=1;
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let usesCustomInserter = 1;
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}
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// JAL and JALX instruction format
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//
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class FJAL16_ins<bits<1> _X, string asmstr,
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InstrItinClass itin>:
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FJAL16<_X, (outs), (ins simm20:$imm),
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!strconcat(asmstr, "\t$imm\n\tnop"),[],
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itin> {
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let isCodeGenOnly=1;
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}
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//
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// EXT-I instruction format
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//
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class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
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FEXT_I16<eop, (outs), (ins brtarget:$imm16),
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!strconcat(asmstr, "\t$imm16"),[], itin>;
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//
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// EXT-I8 instruction format
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//
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class FEXT_I816_ins_base<bits<3> _func, string asmstr,
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string asmstr2, InstrItinClass itin>:
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FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
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[], itin>;
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class FEXT_I816_ins<bits<3> _func, string asmstr,
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InstrItinClass itin>:
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FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>;
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class FEXT_I816_SP_ins<bits<3> _func, string asmstr,
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InstrItinClass itin>:
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FEXT_I816_ins_base<_func, asmstr, "\t$$sp, $imm", itin>;
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//
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// Assembler formats in alphabetical order.
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// Natural and pseudos are mixed together.
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//
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// Compare two registers and place result in CC
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// Implicit use of T8
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//
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// CC-RR Instruction format
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//
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class FCCRR16_ins<string asmstr> :
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MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry\n\tmove\t$cc, $$t8"), []> {
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let isCodeGenOnly=1;
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let usesCustomInserter = 1;
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}
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//
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// EXT-RI instruction format
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//
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class FEXT_RI16_ins_base<bits<5> _op, string asmstr, string asmstr2,
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InstrItinClass itin>:
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FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm),
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!strconcat(asmstr, asmstr2), [], itin>;
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class FEXT_RI16_ins<bits<5> _op, string asmstr,
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InstrItinClass itin>:
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FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
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class FEXT_RI16R_ins_base<bits<5> _op, string asmstr, string asmstr2,
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InstrItinClass itin>:
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FEXT_RI16<_op, (outs ), (ins CPU16Regs:$rx, simm16:$imm),
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!strconcat(asmstr, asmstr2), [], itin>;
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class FEXT_RI16R_ins<bits<5> _op, string asmstr,
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InstrItinClass itin>:
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FEXT_RI16R_ins_base<_op, asmstr, "\t$rx, $imm", itin>;
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class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
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FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
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class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
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InstrItinClass itin>:
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FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
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!strconcat(asmstr, "\t$rx, $imm"), [], itin>;
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class FEXT_2RI16_ins<bits<5> _op, string asmstr,
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InstrItinClass itin>:
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FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
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!strconcat(asmstr, "\t$rx, $imm"), [], itin> {
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let Constraints = "$rx_ = $rx";
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}
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// this has an explicit sp argument that we ignore to work around a problem
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// in the compiler
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class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr,
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InstrItinClass itin>:
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FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPUSPReg:$ry, simm16:$imm),
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!strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
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class FEXT_RI16_SP_Store_explicit_ins<bits<5> _op, string asmstr,
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InstrItinClass itin>:
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FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, CPUSPReg:$ry, simm16:$imm),
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!strconcat(asmstr, "\t$rx, $imm ( $ry ); "), [], itin>;
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//
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// EXT-RRI instruction format
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//
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class FEXT_RRI16_mem_ins<bits<5> op, string asmstr, Operand MemOpnd,
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InstrItinClass itin>:
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FEXT_RRI16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
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!strconcat(asmstr, "\t$ry, $addr"), [], itin>;
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class FEXT_RRI16_mem2_ins<bits<5> op, string asmstr, Operand MemOpnd,
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InstrItinClass itin>:
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FEXT_RRI16<op, (outs ), (ins CPU16Regs:$ry, MemOpnd:$addr),
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!strconcat(asmstr, "\t$ry, $addr"), [], itin>;
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//
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//
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// EXT-RRI-A instruction format
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//
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class FEXT_RRI_A16_mem_ins<bits<1> op, string asmstr, Operand MemOpnd,
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InstrItinClass itin>:
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FEXT_RRI_A16<op, (outs CPU16Regs:$ry), (ins MemOpnd:$addr),
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!strconcat(asmstr, "\t$ry, $addr"), [], itin>;
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//
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// EXT-SHIFT instruction format
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//
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class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
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FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, uimm5:$sa),
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!strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
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//
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// EXT-T8I8
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//
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class FEXT_T8I816_ins<string asmstr, string asmstr2>:
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MipsPseudo16<(outs),
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(ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
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!strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
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!strconcat(asmstr, "\t$imm"))),[]> {
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let isCodeGenOnly=1;
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let usesCustomInserter = 1;
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}
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//
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// EXT-T8I8I
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//
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class FEXT_T8I8I16_ins<string asmstr, string asmstr2>:
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MipsPseudo16<(outs),
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(ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
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!strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
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!strconcat(asmstr, "\t$targ"))), []> {
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let isCodeGenOnly=1;
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let usesCustomInserter = 1;
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}
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//
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//
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// I8_MOVR32 instruction format (used only by the MOVR32 instructio
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//
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class FI8_MOVR3216_ins<string asmstr, InstrItinClass itin>:
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FI8_MOVR3216<(outs CPU16Regs:$rz), (ins GPR32:$r32),
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!strconcat(asmstr, "\t$rz, $r32"), [], itin>;
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//
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// I8_MOV32R instruction format (used only by MOV32R instruction)
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//
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class FI8_MOV32R16_ins<string asmstr, InstrItinClass itin>:
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FI8_MOV32R16<(outs GPR32:$r32), (ins CPU16Regs:$rz),
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!strconcat(asmstr, "\t$r32, $rz"), [], itin>;
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//
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// This are pseudo formats for multiply
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// This first one can be changed to non pseudo now.
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//
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// MULT
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//
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class FMULT16_ins<string asmstr, InstrItinClass itin> :
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MipsPseudo16<(outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry"), []>;
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//
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// MULT-LO
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//
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class FMULT16_LO_ins<string asmstr, InstrItinClass itin> :
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MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry\n\tmflo\t$rz"), []> {
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let isCodeGenOnly=1;
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}
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//
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// RR-type instruction format
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//
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class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
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FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry"), [], itin> {
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}
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class FRRBreakNull16_ins<string asmstr, InstrItinClass itin> :
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FRRBreak16<(outs), (ins), asmstr, [], itin> {
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let Code=0;
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}
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class FRR16R_ins<bits<5> f, string asmstr, InstrItinClass itin> :
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FRR16<f, (outs), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry"), [], itin> {
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}
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class FRRTR16_ins<string asmstr> :
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MipsPseudo16<(outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), []> ;
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//
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// maybe refactor but need a $zero as a dummy first parameter
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//
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class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
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FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
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class FUnaryRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
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FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry"), [], itin> ;
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class FRR16_M_ins<bits<5> f, string asmstr,
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InstrItinClass itin> :
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FRR16<f, (outs CPU16Regs:$rx), (ins),
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!strconcat(asmstr, "\t$rx"), [], itin>;
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class FRxRxRy16_ins<bits<5> f, string asmstr,
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InstrItinClass itin> :
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FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rz, $ry"),
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[], itin> {
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let Constraints = "$rx = $rz";
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}
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let rx=0 in
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class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
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string asmstr, InstrItinClass itin>:
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FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
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[], itin> ;
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class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
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string asmstr, InstrItinClass itin>:
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FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
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!strconcat(asmstr, "\t $rx"), [], itin> ;
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class FRR_SF16_ins
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<bits<5> _funct, bits<3> _subfunc,
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string asmstr, InstrItinClass itin>:
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FRR_SF16<_funct, _subfunc, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_),
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!strconcat(asmstr, "\t $rx"),
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[], itin> {
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let Constraints = "$rx_ = $rx";
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}
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//
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// RRR-type instruction format
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//
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class FRRR16_ins<bits<2> _f, string asmstr, InstrItinClass itin> :
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FRRR16<_f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rz, $rx, $ry"), [], itin>;
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//
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// These Sel patterns support the generation of conditional move
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// pseudo instructions.
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//
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// The nomenclature uses the components making up the pseudo and may
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// be a bit counter intuitive when compared with the end result we seek.
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// For example using a bqez in the example directly below results in the
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// conditional move being done if the tested register is not zero.
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// I considered in easier to check by keeping the pseudo consistent with
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// it's components but it could have been done differently.
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//
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// The simplest case is when can test and operand directly and do the
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// conditional move based on a simple mips16 conditional
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// branch instruction.
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// for example:
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// if $op == beqz or bnez:
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//
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// $op1 $rt, .+4
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// move $rd, $rs
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//
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// if $op == beqz, then if $rt != 0, then the conditional assignment
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// $rd = $rs is done.
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// if $op == bnez, then if $rt == 0, then the conditional assignment
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// $rd = $rs is done.
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//
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// So this pseudo class only has one operand, i.e. op
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//
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class Sel<string op>:
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MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
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CPU16Regs:$rt),
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!strconcat(op, "\t$rt, .+4\n\t\n\tmove $rd, $rs"), []> {
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//let isCodeGenOnly=1;
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let Constraints = "$rd = $rd_";
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let usesCustomInserter = 1;
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}
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//
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// The next two instruction classes allow for an operand which tests
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// two operands and returns a value in register T8 and
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//then does a conditional branch based on the value of T8
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//
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// op2 can be cmpi or slti/sltiu
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// op1 can bteqz or btnez
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// the operands for op2 are a register and a signed constant
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//
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// $op2 $t, $imm ;test register t and branch conditionally
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// $op1 .+4 ;op1 is a conditional branch
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// move $rd, $rs
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//
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//
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class SeliT<string op1, string op2>:
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MipsPseudo16<(outs CPU16Regs:$rd_), (ins CPU16Regs:$rd, CPU16Regs:$rs,
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CPU16Regs:$rl, simm16:$imm),
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!strconcat(op2,
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!strconcat("\t$rl, $imm\n\t",
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!strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
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let isCodeGenOnly=1;
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let Constraints = "$rd = $rd_";
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let usesCustomInserter = 1;
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}
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//
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// op2 can be cmp or slt/sltu
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// op1 can be bteqz or btnez
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// the operands for op2 are two registers
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// op1 is a conditional branch
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//
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//
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// $op2 $rl, $rr ;test registers rl,rr
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// $op1 .+4 ;op2 is a conditional branch
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|
// move $rd, $rs
|
|
//
|
|
//
|
|
class SelT<string op1, string op2>:
|
|
MipsPseudo16<(outs CPU16Regs:$rd_),
|
|
(ins CPU16Regs:$rd, CPU16Regs:$rs,
|
|
CPU16Regs:$rl, CPU16Regs:$rr),
|
|
!strconcat(op2,
|
|
!strconcat("\t$rl, $rr\n\t",
|
|
!strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
|
|
let isCodeGenOnly=1;
|
|
let Constraints = "$rd = $rd_";
|
|
let usesCustomInserter = 1;
|
|
}
|
|
|
|
//
|
|
// 32 bit constant
|
|
//
|
|
def imm32: Operand<i32>;
|
|
|
|
def Constant32:
|
|
MipsPseudo16<(outs), (ins imm32:$imm), "\t.word $imm", []>;
|
|
|
|
def LwConstant32:
|
|
MipsPseudo16<(outs CPU16Regs:$rx), (ins imm32:$imm),
|
|
"lw\t$rx, 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t$imm\n2:", []>;
|
|
|
|
|
|
//
|
|
// Some general instruction class info
|
|
//
|
|
//
|
|
|
|
class ArithLogic16Defs<bit isCom=0> {
|
|
bits<5> shamt = 0;
|
|
bit isCommutable = isCom;
|
|
bit isReMaterializable = 1;
|
|
bit neverHasSideEffects = 1;
|
|
}
|
|
|
|
class branch16 {
|
|
bit isBranch = 1;
|
|
bit isTerminator = 1;
|
|
bit isBarrier = 1;
|
|
}
|
|
|
|
class cbranch16 {
|
|
bit isBranch = 1;
|
|
bit isTerminator = 1;
|
|
}
|
|
|
|
class MayLoad {
|
|
bit mayLoad = 1;
|
|
}
|
|
|
|
class MayStore {
|
|
bit mayStore = 1;
|
|
}
|
|
//
|
|
|
|
|
|
// Format: ADDIU rx, immediate MIPS16e
|
|
// Purpose: Add Immediate Unsigned Word (2-Operand, Extended)
|
|
// To add a constant to a 32-bit integer.
|
|
//
|
|
def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>;
|
|
|
|
def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>,
|
|
ArithLogic16Defs<0> {
|
|
let AddedComplexity = 5;
|
|
}
|
|
def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>,
|
|
ArithLogic16Defs<0> {
|
|
let isCodeGenOnly = 1;
|
|
}
|
|
|
|
def AddiuRxRyOffMemX16:
|
|
FEXT_RRI_A16_mem_ins<0, "addiu", mem16_ea, IIAlu>;
|
|
|
|
//
|
|
|
|
// Format: ADDIU rx, pc, immediate MIPS16e
|
|
// Purpose: Add Immediate Unsigned Word (3-Operand, PC-Relative, Extended)
|
|
// To add a constant to the program counter.
|
|
//
|
|
def AddiuRxPcImmX16: FEXT_RI16_PC_ins<0b00001, "addiu", IIAlu>;
|
|
|
|
//
|
|
// Format: ADDIU sp, immediate MIPS16e
|
|
// Purpose: Add Immediate Unsigned Word (2-Operand, SP-Relative, Extended)
|
|
// To add a constant to the stack pointer.
|
|
//
|
|
def AddiuSpImm16
|
|
: FI816_SP_ins<0b011, "addiu", IIAlu> {
|
|
let Defs = [SP];
|
|
let Uses = [SP];
|
|
let AddedComplexity = 5;
|
|
}
|
|
|
|
def AddiuSpImmX16
|
|
: FEXT_I816_SP_ins<0b011, "addiu", IIAlu> {
|
|
let Defs = [SP];
|
|
let Uses = [SP];
|
|
}
|
|
|
|
//
|
|
// Format: ADDU rz, rx, ry MIPS16e
|
|
// Purpose: Add Unsigned Word (3-Operand)
|
|
// To add 32-bit integers.
|
|
//
|
|
|
|
def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
|
|
|
|
//
|
|
// Format: AND rx, ry MIPS16e
|
|
// Purpose: AND
|
|
// To do a bitwise logical AND.
|
|
|
|
def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
|
|
|
|
|
|
//
|
|
// Format: BEQZ rx, offset MIPS16e
|
|
// Purpose: Branch on Equal to Zero
|
|
// To test a GPR then do a PC-relative conditional branch.
|
|
//
|
|
def BeqzRxImm16: FRI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
|
|
|
|
|
|
//
|
|
// Format: BEQZ rx, offset MIPS16e
|
|
// Purpose: Branch on Equal to Zero (Extended)
|
|
// To test a GPR then do a PC-relative conditional branch.
|
|
//
|
|
def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
|
|
|
|
// Format: B offset MIPS16e
|
|
// Purpose: Unconditional Branch
|
|
// To do an unconditional PC-relative branch.
|
|
//
|
|
def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16;
|
|
|
|
//
|
|
// Format: BNEZ rx, offset MIPS16e
|
|
// Purpose: Branch on Not Equal to Zero
|
|
// To test a GPR then do a PC-relative conditional branch.
|
|
//
|
|
def BnezRxImm16: FRI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
|
|
|
|
//
|
|
// Format: BNEZ rx, offset MIPS16e
|
|
// Purpose: Branch on Not Equal to Zero (Extended)
|
|
// To test a GPR then do a PC-relative conditional branch.
|
|
//
|
|
def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
|
|
|
|
|
|
//
|
|
//Format: BREAK immediate
|
|
// Purpose: Breakpoint
|
|
// To cause a Breakpoint exception.
|
|
|
|
def Break16: FRRBreakNull16_ins<"break 0", NoItinerary>;
|
|
//
|
|
// Format: BTEQZ offset MIPS16e
|
|
// Purpose: Branch on T Equal to Zero (Extended)
|
|
// To test special register T then do a PC-relative conditional branch.
|
|
//
|
|
def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 {
|
|
let Uses = [T8];
|
|
}
|
|
|
|
def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16;
|
|
|
|
def BteqzT8CmpiX16: FEXT_T8I8I16_ins<"bteqz", "cmpi">,
|
|
cbranch16;
|
|
|
|
def BteqzT8SltX16: FEXT_T8I816_ins<"bteqz", "slt">, cbranch16;
|
|
|
|
def BteqzT8SltuX16: FEXT_T8I816_ins<"bteqz", "sltu">, cbranch16;
|
|
|
|
def BteqzT8SltiX16: FEXT_T8I8I16_ins<"bteqz", "slti">, cbranch16;
|
|
|
|
def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">,
|
|
cbranch16;
|
|
|
|
//
|
|
// Format: BTNEZ offset MIPS16e
|
|
// Purpose: Branch on T Not Equal to Zero (Extended)
|
|
// To test special register T then do a PC-relative conditional branch.
|
|
//
|
|
def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 {
|
|
let Uses = [T8];
|
|
}
|
|
|
|
def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16;
|
|
|
|
def BtnezT8CmpiX16: FEXT_T8I8I16_ins<"btnez", "cmpi">, cbranch16;
|
|
|
|
def BtnezT8SltX16: FEXT_T8I816_ins<"btnez", "slt">, cbranch16;
|
|
|
|
def BtnezT8SltuX16: FEXT_T8I816_ins<"btnez", "sltu">, cbranch16;
|
|
|
|
def BtnezT8SltiX16: FEXT_T8I8I16_ins<"btnez", "slti">, cbranch16;
|
|
|
|
def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">,
|
|
cbranch16;
|
|
|
|
//
|
|
// Format: CMP rx, ry MIPS16e
|
|
// Purpose: Compare
|
|
// To compare the contents of two GPRs.
|
|
//
|
|
def CmpRxRy16: FRR16R_ins<0b01010, "cmp", IIAlu> {
|
|
let Defs = [T8];
|
|
}
|
|
|
|
//
|
|
// Format: CMPI rx, immediate MIPS16e
|
|
// Purpose: Compare Immediate
|
|
// To compare a constant with the contents of a GPR.
|
|
//
|
|
def CmpiRxImm16: FRI16R_ins<0b01110, "cmpi", IIAlu> {
|
|
let Defs = [T8];
|
|
}
|
|
|
|
//
|
|
// Format: CMPI rx, immediate MIPS16e
|
|
// Purpose: Compare Immediate (Extended)
|
|
// To compare a constant with the contents of a GPR.
|
|
//
|
|
def CmpiRxImmX16: FEXT_RI16R_ins<0b01110, "cmpi", IIAlu> {
|
|
let Defs = [T8];
|
|
}
|
|
|
|
|
|
//
|
|
// Format: DIV rx, ry MIPS16e
|
|
// Purpose: Divide Word
|
|
// To divide 32-bit signed integers.
|
|
//
|
|
def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
|
|
let Defs = [HI0, LO0];
|
|
}
|
|
|
|
//
|
|
// Format: DIVU rx, ry MIPS16e
|
|
// Purpose: Divide Unsigned Word
|
|
// To divide 32-bit unsigned integers.
|
|
//
|
|
def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
|
|
let Defs = [HI0, LO0];
|
|
}
|
|
//
|
|
// Format: JAL target MIPS16e
|
|
// Purpose: Jump and Link
|
|
// To execute a procedure call within the current 256 MB-aligned
|
|
// region and preserve the current ISA.
|
|
//
|
|
|
|
def Jal16 : FJAL16_ins<0b0, "jal", IIAlu> {
|
|
let hasDelaySlot = 0; // not true, but we add the nop for now
|
|
let isCall=1;
|
|
}
|
|
|
|
//
|
|
// Format: JR ra MIPS16e
|
|
// Purpose: Jump Register Through Register ra
|
|
// To execute a branch to the instruction address in the return
|
|
// address register.
|
|
//
|
|
|
|
def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> {
|
|
let isBranch = 1;
|
|
let isIndirectBranch = 1;
|
|
let hasDelaySlot = 1;
|
|
let isTerminator=1;
|
|
let isBarrier=1;
|
|
}
|
|
|
|
def JrcRa16: FRR16_JALRC_RA_only_ins<1, 1, "jrc", IIAlu> {
|
|
let isBranch = 1;
|
|
let isIndirectBranch = 1;
|
|
let isTerminator=1;
|
|
let isBarrier=1;
|
|
}
|
|
|
|
def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
|
|
let isBranch = 1;
|
|
let isIndirectBranch = 1;
|
|
let isTerminator=1;
|
|
let isBarrier=1;
|
|
}
|
|
//
|
|
// Format: LB ry, offset(rx) MIPS16e
|
|
// Purpose: Load Byte (Extended)
|
|
// To load a byte from memory as a signed value.
|
|
//
|
|
def LbRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lb", mem16, IILoad>, MayLoad{
|
|
let isCodeGenOnly = 1;
|
|
}
|
|
|
|
//
|
|
// Format: LBU ry, offset(rx) MIPS16e
|
|
// Purpose: Load Byte Unsigned (Extended)
|
|
// To load a byte from memory as a unsigned value.
|
|
//
|
|
def LbuRxRyOffMemX16:
|
|
FEXT_RRI16_mem_ins<0b10100, "lbu", mem16, IILoad>, MayLoad {
|
|
let isCodeGenOnly = 1;
|
|
}
|
|
|
|
//
|
|
// Format: LH ry, offset(rx) MIPS16e
|
|
// Purpose: Load Halfword signed (Extended)
|
|
// To load a halfword from memory as a signed value.
|
|
//
|
|
def LhRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10100, "lh", mem16, IILoad>, MayLoad{
|
|
let isCodeGenOnly = 1;
|
|
}
|
|
|
|
//
|
|
// Format: LHU ry, offset(rx) MIPS16e
|
|
// Purpose: Load Halfword unsigned (Extended)
|
|
// To load a halfword from memory as an unsigned value.
|
|
//
|
|
def LhuRxRyOffMemX16:
|
|
FEXT_RRI16_mem_ins<0b10100, "lhu", mem16, IILoad>, MayLoad {
|
|
let isCodeGenOnly = 1;
|
|
}
|
|
|
|
//
|
|
// Format: LI rx, immediate MIPS16e
|
|
// Purpose: Load Immediate
|
|
// To load a constant into a GPR.
|
|
//
|
|
def LiRxImm16: FRI16_ins<0b01101, "li", IIAlu>;
|
|
|
|
//
|
|
// Format: LI rx, immediate MIPS16e
|
|
// Purpose: Load Immediate (Extended)
|
|
// To load a constant into a GPR.
|
|
//
|
|
def LiRxImmX16: FEXT_RI16_ins<0b01101, "li", IIAlu>;
|
|
|
|
def LiRxImmAlignX16: FEXT_RI16_ins<0b01101, ".align 2\n\tli", IIAlu> {
|
|
let isCodeGenOnly = 1;
|
|
}
|
|
|
|
//
|
|
// Format: LW ry, offset(rx) MIPS16e
|
|
// Purpose: Load Word (Extended)
|
|
// To load a word from memory as a signed value.
|
|
//
|
|
def LwRxRyOffMemX16: FEXT_RRI16_mem_ins<0b10011, "lw", mem16, IILoad>, MayLoad{
|
|
let isCodeGenOnly = 1;
|
|
}
|
|
|
|
// Format: LW rx, offset(sp) MIPS16e
|
|
// Purpose: Load Word (SP-Relative, Extended)
|
|
// To load an SP-relative word from memory as a signed value.
|
|
//
|
|
def LwRxSpImmX16: FEXT_RI16_SP_explicit_ins<0b10110, "lw", IILoad>, MayLoad{
|
|
let Uses = [SP];
|
|
}
|
|
|
|
//
|
|
// Format: MOVE r32, rz MIPS16e
|
|
// Purpose: Move
|
|
// To move the contents of a GPR to a GPR.
|
|
//
|
|
def Move32R16: FI8_MOV32R16_ins<"move", IIAlu>;
|
|
|
|
//
|
|
// Format: MOVE ry, r32 MIPS16e
|
|
//Purpose: Move
|
|
// To move the contents of a GPR to a GPR.
|
|
//
|
|
def MoveR3216: FI8_MOVR3216_ins<"move", IIAlu>;
|
|
|
|
//
|
|
// Format: MFHI rx MIPS16e
|
|
// Purpose: Move From HI Register
|
|
// To copy the special purpose HI register to a GPR.
|
|
//
|
|
def Mfhi16: FRR16_M_ins<0b10000, "mfhi", IIAlu> {
|
|
let Uses = [HI0];
|
|
let neverHasSideEffects = 1;
|
|
}
|
|
|
|
//
|
|
// Format: MFLO rx MIPS16e
|
|
// Purpose: Move From LO Register
|
|
// To copy the special purpose LO register to a GPR.
|
|
//
|
|
def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> {
|
|
let Uses = [LO0];
|
|
let neverHasSideEffects = 1;
|
|
}
|
|
|
|
//
|
|
// Pseudo Instruction for mult
|
|
//
|
|
def MultRxRy16: FMULT16_ins<"mult", IIAlu> {
|
|
let isCommutable = 1;
|
|
let neverHasSideEffects = 1;
|
|
let Defs = [HI0, LO0];
|
|
}
|
|
|
|
def MultuRxRy16: FMULT16_ins<"multu", IIAlu> {
|
|
let isCommutable = 1;
|
|
let neverHasSideEffects = 1;
|
|
let Defs = [HI0, LO0];
|
|
}
|
|
|
|
//
|
|
// Format: MULT rx, ry MIPS16e
|
|
// Purpose: Multiply Word
|
|
// To multiply 32-bit signed integers.
|
|
//
|
|
def MultRxRyRz16: FMULT16_LO_ins<"mult", IIAlu> {
|
|
let isCommutable = 1;
|
|
let neverHasSideEffects = 1;
|
|
let Defs = [HI0, LO0];
|
|
}
|
|
|
|
//
|
|
// Format: MULTU rx, ry MIPS16e
|
|
// Purpose: Multiply Unsigned Word
|
|
// To multiply 32-bit unsigned integers.
|
|
//
|
|
def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> {
|
|
let isCommutable = 1;
|
|
let neverHasSideEffects = 1;
|
|
let Defs = [HI0, LO0];
|
|
}
|
|
|
|
//
|
|
// Format: NEG rx, ry MIPS16e
|
|
// Purpose: Negate
|
|
// To negate an integer value.
|
|
//
|
|
def NegRxRy16: FUnaryRR16_ins<0b11101, "neg", IIAlu>;
|
|
|
|
//
|
|
// Format: NOT rx, ry MIPS16e
|
|
// Purpose: Not
|
|
// To complement an integer value
|
|
//
|
|
def NotRxRy16: FUnaryRR16_ins<0b01111, "not", IIAlu>;
|
|
|
|
//
|
|
// Format: OR rx, ry MIPS16e
|
|
// Purpose: Or
|
|
// To do a bitwise logical OR.
|
|
//
|
|
def OrRxRxRy16: FRxRxRy16_ins<0b01101, "or", IIAlu>, ArithLogic16Defs<1>;
|
|
|
|
//
|
|
// Format: RESTORE {ra,}{s0/s1/s0-1,}{framesize}
|
|
// (All args are optional) MIPS16e
|
|
// Purpose: Restore Registers and Deallocate Stack Frame
|
|
// To deallocate a stack frame before exit from a subroutine,
|
|
// restoring return address and static registers, and adjusting
|
|
// stack
|
|
//
|
|
|
|
// fixed form for restoring RA and the frame
|
|
// for direct object emitter, encoding needs to be adjusted for the
|
|
// frame size
|
|
//
|
|
let ra=1, s=0,s0=1,s1=1 in
|
|
def RestoreRaF16:
|
|
FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
|
|
"restore\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IILoad >, MayLoad {
|
|
let isCodeGenOnly = 1;
|
|
let Defs = [S0, S1, S2, RA, SP];
|
|
let Uses = [SP];
|
|
}
|
|
|
|
// Use Restore to increment SP since SP is not a Mip 16 register, this
|
|
// is an easy way to do that which does not require a register.
|
|
//
|
|
let ra=0, s=0,s0=0,s1=0 in
|
|
def RestoreIncSpF16:
|
|
FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
|
|
"restore\t$frame_size", [], IILoad >, MayLoad {
|
|
let isCodeGenOnly = 1;
|
|
let Defs = [SP];
|
|
let Uses = [SP];
|
|
}
|
|
|
|
//
|
|
// Format: SAVE {ra,}{s0/s1/s0-1,}{framesize} (All arguments are optional)
|
|
// MIPS16e
|
|
// Purpose: Save Registers and Set Up Stack Frame
|
|
// To set up a stack frame on entry to a subroutine,
|
|
// saving return address and static registers, and adjusting stack
|
|
//
|
|
let ra=1, s=1,s0=1,s1=1 in
|
|
def SaveRaF16:
|
|
FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
|
|
"save\t$$ra, $$s0, $$s1, $$s2, $frame_size", [], IIStore >, MayStore {
|
|
let isCodeGenOnly = 1;
|
|
let Uses = [RA, SP, S0, S1, S2];
|
|
let Defs = [SP];
|
|
}
|
|
|
|
//
|
|
// Use Save to decrement the SP by a constant since SP is not
|
|
// a Mips16 register.
|
|
//
|
|
let ra=0, s=0,s0=0,s1=0 in
|
|
def SaveDecSpF16:
|
|
FI8_SVRS16<0b1, (outs), (ins uimm16:$frame_size),
|
|
"save\t$frame_size", [], IIStore >, MayStore {
|
|
let isCodeGenOnly = 1;
|
|
let Uses = [SP];
|
|
let Defs = [SP];
|
|
}
|
|
//
|
|
// Format: SB ry, offset(rx) MIPS16e
|
|
// Purpose: Store Byte (Extended)
|
|
// To store a byte to memory.
|
|
//
|
|
def SbRxRyOffMemX16:
|
|
FEXT_RRI16_mem2_ins<0b11000, "sb", mem16, IIStore>, MayStore;
|
|
|
|
//
|
|
// Format: SEB rx MIPS16e
|
|
// Purpose: Sign-Extend Byte
|
|
// Sign-extend least significant byte in register rx.
|
|
//
|
|
def SebRx16
|
|
: FRR_SF16_ins<0b10001, 0b100, "seb", IIAlu>;
|
|
|
|
//
|
|
// Format: SEH rx MIPS16e
|
|
// Purpose: Sign-Extend Halfword
|
|
// Sign-extend least significant word in register rx.
|
|
//
|
|
def SehRx16
|
|
: FRR_SF16_ins<0b10001, 0b101, "seh", IIAlu>;
|
|
|
|
//
|
|
// The Sel(T) instructions are pseudos
|
|
// T means that they use T8 implicitly.
|
|
//
|
|
//
|
|
// Format: SelBeqZ rd, rs, rt
|
|
// Purpose: if rt==0, do nothing
|
|
// else rs = rt
|
|
//
|
|
def SelBeqZ: Sel<"beqz">;
|
|
|
|
//
|
|
// Format: SelTBteqZCmp rd, rs, rl, rr
|
|
// Purpose: b = Cmp rl, rr.
|
|
// If b==0 then do nothing.
|
|
// if b!=0 then rd = rs
|
|
//
|
|
def SelTBteqZCmp: SelT<"bteqz", "cmp">;
|
|
|
|
//
|
|
// Format: SelTBteqZCmpi rd, rs, rl, rr
|
|
// Purpose: b = Cmpi rl, imm.
|
|
// If b==0 then do nothing.
|
|
// if b!=0 then rd = rs
|
|
//
|
|
def SelTBteqZCmpi: SeliT<"bteqz", "cmpi">;
|
|
|
|
//
|
|
// Format: SelTBteqZSlt rd, rs, rl, rr
|
|
// Purpose: b = Slt rl, rr.
|
|
// If b==0 then do nothing.
|
|
// if b!=0 then rd = rs
|
|
//
|
|
def SelTBteqZSlt: SelT<"bteqz", "slt">;
|
|
|
|
//
|
|
// Format: SelTBteqZSlti rd, rs, rl, rr
|
|
// Purpose: b = Slti rl, imm.
|
|
// If b==0 then do nothing.
|
|
// if b!=0 then rd = rs
|
|
//
|
|
def SelTBteqZSlti: SeliT<"bteqz", "slti">;
|
|
|
|
//
|
|
// Format: SelTBteqZSltu rd, rs, rl, rr
|
|
// Purpose: b = Sltu rl, rr.
|
|
// If b==0 then do nothing.
|
|
// if b!=0 then rd = rs
|
|
//
|
|
def SelTBteqZSltu: SelT<"bteqz", "sltu">;
|
|
|
|
//
|
|
// Format: SelTBteqZSltiu rd, rs, rl, rr
|
|
// Purpose: b = Sltiu rl, imm.
|
|
// If b==0 then do nothing.
|
|
// if b!=0 then rd = rs
|
|
//
|
|
def SelTBteqZSltiu: SeliT<"bteqz", "sltiu">;
|
|
|
|
//
|
|
// Format: SelBnez rd, rs, rt
|
|
// Purpose: if rt!=0, do nothing
|
|
// else rs = rt
|
|
//
|
|
def SelBneZ: Sel<"bnez">;
|
|
|
|
//
|
|
// Format: SelTBtneZCmp rd, rs, rl, rr
|
|
// Purpose: b = Cmp rl, rr.
|
|
// If b!=0 then do nothing.
|
|
// if b0=0 then rd = rs
|
|
//
|
|
def SelTBtneZCmp: SelT<"btnez", "cmp">;
|
|
|
|
//
|
|
// Format: SelTBtnezCmpi rd, rs, rl, rr
|
|
// Purpose: b = Cmpi rl, imm.
|
|
// If b!=0 then do nothing.
|
|
// if b==0 then rd = rs
|
|
//
|
|
def SelTBtneZCmpi: SeliT<"btnez", "cmpi">;
|
|
|
|
//
|
|
// Format: SelTBtneZSlt rd, rs, rl, rr
|
|
// Purpose: b = Slt rl, rr.
|
|
// If b!=0 then do nothing.
|
|
// if b==0 then rd = rs
|
|
//
|
|
def SelTBtneZSlt: SelT<"btnez", "slt">;
|
|
|
|
//
|
|
// Format: SelTBtneZSlti rd, rs, rl, rr
|
|
// Purpose: b = Slti rl, imm.
|
|
// If b!=0 then do nothing.
|
|
// if b==0 then rd = rs
|
|
//
|
|
def SelTBtneZSlti: SeliT<"btnez", "slti">;
|
|
|
|
//
|
|
// Format: SelTBtneZSltu rd, rs, rl, rr
|
|
// Purpose: b = Sltu rl, rr.
|
|
// If b!=0 then do nothing.
|
|
// if b==0 then rd = rs
|
|
//
|
|
def SelTBtneZSltu: SelT<"btnez", "sltu">;
|
|
|
|
//
|
|
// Format: SelTBtneZSltiu rd, rs, rl, rr
|
|
// Purpose: b = Slti rl, imm.
|
|
// If b!=0 then do nothing.
|
|
// if b==0 then rd = rs
|
|
//
|
|
def SelTBtneZSltiu: SeliT<"btnez", "sltiu">;
|
|
//
|
|
//
|
|
// Format: SH ry, offset(rx) MIPS16e
|
|
// Purpose: Store Halfword (Extended)
|
|
// To store a halfword to memory.
|
|
//
|
|
def ShRxRyOffMemX16:
|
|
FEXT_RRI16_mem2_ins<0b11001, "sh", mem16, IIStore>, MayStore;
|
|
|
|
//
|
|
// Format: SLL rx, ry, sa MIPS16e
|
|
// Purpose: Shift Word Left Logical (Extended)
|
|
// To execute a left-shift of a word by a fixed number of bits—0 to 31 bits.
|
|
//
|
|
def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>;
|
|
|
|
//
|
|
// Format: SLLV ry, rx MIPS16e
|
|
// Purpose: Shift Word Left Logical Variable
|
|
// To execute a left-shift of a word by a variable number of bits.
|
|
//
|
|
def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>;
|
|
|
|
// Format: SLTI rx, immediate MIPS16e
|
|
// Purpose: Set on Less Than Immediate
|
|
// To record the result of a less-than comparison with a constant.
|
|
//
|
|
//
|
|
def SltiRxImm16: FRI16R_ins<0b01010, "slti", IIAlu> {
|
|
let Defs = [T8];
|
|
}
|
|
|
|
//
|
|
// Format: SLTI rx, immediate MIPS16e
|
|
// Purpose: Set on Less Than Immediate (Extended)
|
|
// To record the result of a less-than comparison with a constant.
|
|
//
|
|
//
|
|
def SltiRxImmX16: FEXT_RI16R_ins<0b01010, "slti", IIAlu> {
|
|
let Defs = [T8];
|
|
}
|
|
|
|
def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">;
|
|
|
|
// Format: SLTIU rx, immediate MIPS16e
|
|
// Purpose: Set on Less Than Immediate Unsigned
|
|
// To record the result of a less-than comparison with a constant.
|
|
//
|
|
//
|
|
def SltiuRxImm16: FRI16R_ins<0b01011, "sltiu", IIAlu> {
|
|
let Defs = [T8];
|
|
}
|
|
|
|
//
|
|
// Format: SLTI rx, immediate MIPS16e
|
|
// Purpose: Set on Less Than Immediate Unsigned (Extended)
|
|
// To record the result of a less-than comparison with a constant.
|
|
//
|
|
//
|
|
def SltiuRxImmX16: FEXT_RI16R_ins<0b01011, "sltiu", IIAlu> {
|
|
let Defs = [T8];
|
|
}
|
|
//
|
|
// Format: SLTIU rx, immediate MIPS16e
|
|
// Purpose: Set on Less Than Immediate Unsigned (Extended)
|
|
// To record the result of a less-than comparison with a constant.
|
|
//
|
|
def SltiuCCRxImmX16: FEXT_CCRXI16_ins<"sltiu">;
|
|
|
|
//
|
|
// Format: SLT rx, ry MIPS16e
|
|
// Purpose: Set on Less Than
|
|
// To record the result of a less-than comparison.
|
|
//
|
|
def SltRxRy16: FRR16R_ins<0b00010, "slt", IIAlu>{
|
|
let Defs = [T8];
|
|
}
|
|
|
|
def SltCCRxRy16: FCCRR16_ins<"slt">;
|
|
|
|
// Format: SLTU rx, ry MIPS16e
|
|
// Purpose: Set on Less Than Unsigned
|
|
// To record the result of an unsigned less-than comparison.
|
|
//
|
|
def SltuRxRy16: FRR16R_ins<0b00011, "sltu", IIAlu>{
|
|
let Defs = [T8];
|
|
}
|
|
|
|
def SltuRxRyRz16: FRRTR16_ins<"sltu"> {
|
|
let isCodeGenOnly=1;
|
|
let Defs = [T8];
|
|
}
|
|
|
|
|
|
def SltuCCRxRy16: FCCRR16_ins<"sltu">;
|
|
//
|
|
// Format: SRAV ry, rx MIPS16e
|
|
// Purpose: Shift Word Right Arithmetic Variable
|
|
// To execute an arithmetic right-shift of a word by a variable
|
|
// number of bits.
|
|
//
|
|
def SravRxRy16: FRxRxRy16_ins<0b00111, "srav", IIAlu>;
|
|
|
|
|
|
//
|
|
// Format: SRA rx, ry, sa MIPS16e
|
|
// Purpose: Shift Word Right Arithmetic (Extended)
|
|
// To execute an arithmetic right-shift of a word by a fixed
|
|
// number of bits—1 to 8 bits.
|
|
//
|
|
def SraX16: FEXT_SHIFT16_ins<0b11, "sra", IIAlu>;
|
|
|
|
|
|
//
|
|
// Format: SRLV ry, rx MIPS16e
|
|
// Purpose: Shift Word Right Logical Variable
|
|
// To execute a logical right-shift of a word by a variable
|
|
// number of bits.
|
|
//
|
|
def SrlvRxRy16: FRxRxRy16_ins<0b00110, "srlv", IIAlu>;
|
|
|
|
|
|
//
|
|
// Format: SRL rx, ry, sa MIPS16e
|
|
// Purpose: Shift Word Right Logical (Extended)
|
|
// To execute a logical right-shift of a word by a fixed
|
|
// number of bits—1 to 31 bits.
|
|
//
|
|
def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
|
|
|
|
//
|
|
// Format: SUBU rz, rx, ry MIPS16e
|
|
// Purpose: Subtract Unsigned Word
|
|
// To subtract 32-bit integers
|
|
//
|
|
def SubuRxRyRz16: FRRR16_ins<0b11, "subu", IIAlu>, ArithLogic16Defs<0>;
|
|
|
|
//
|
|
// Format: SW ry, offset(rx) MIPS16e
|
|
// Purpose: Store Word (Extended)
|
|
// To store a word to memory.
|
|
//
|
|
def SwRxRyOffMemX16:
|
|
FEXT_RRI16_mem2_ins<0b11011, "sw", mem16, IIStore>, MayStore;
|
|
|
|
//
|
|
// Format: SW rx, offset(sp) MIPS16e
|
|
// Purpose: Store Word rx (SP-Relative)
|
|
// To store an SP-relative word to memory.
|
|
//
|
|
def SwRxSpImmX16: FEXT_RI16_SP_Store_explicit_ins
|
|
<0b11010, "sw", IIStore>, MayStore;
|
|
|
|
//
|
|
//
|
|
// Format: XOR rx, ry MIPS16e
|
|
// Purpose: Xor
|
|
// To do a bitwise logical XOR.
|
|
//
|
|
def XorRxRxRy16: FRxRxRy16_ins<0b01110, "xor", IIAlu>, ArithLogic16Defs<1>;
|
|
|
|
class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
|
|
let Predicates = [InMips16Mode];
|
|
}
|
|
|
|
// Unary Arith/Logic
|
|
//
|
|
class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
|
|
Mips16Pat<(OpNode CPU16Regs:$r),
|
|
(I CPU16Regs:$r)>;
|
|
|
|
def: ArithLogicU_pat<not, NotRxRy16>;
|
|
def: ArithLogicU_pat<ineg, NegRxRy16>;
|
|
|
|
class ArithLogic16_pat<SDNode OpNode, Instruction I> :
|
|
Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
|
|
(I CPU16Regs:$l, CPU16Regs:$r)>;
|
|
|
|
def: ArithLogic16_pat<add, AdduRxRyRz16>;
|
|
def: ArithLogic16_pat<and, AndRxRxRy16>;
|
|
def: ArithLogic16_pat<mul, MultRxRyRz16>;
|
|
def: ArithLogic16_pat<or, OrRxRxRy16>;
|
|
def: ArithLogic16_pat<sub, SubuRxRyRz16>;
|
|
def: ArithLogic16_pat<xor, XorRxRxRy16>;
|
|
|
|
// Arithmetic and logical instructions with 2 register operands.
|
|
|
|
class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> :
|
|
Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
|
|
(I CPU16Regs:$in, imm_type:$imm)>;
|
|
|
|
def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>;
|
|
def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
|
|
def: ArithLogicI16_pat<shl, immZExt5, SllX16>;
|
|
def: ArithLogicI16_pat<srl, immZExt5, SrlX16>;
|
|
def: ArithLogicI16_pat<sra, immZExt5, SraX16>;
|
|
|
|
class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
|
|
Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
|
|
(I CPU16Regs:$r, CPU16Regs:$ra)>;
|
|
|
|
def: shift_rotate_reg16_pat<shl, SllvRxRy16>;
|
|
def: shift_rotate_reg16_pat<sra, SravRxRy16>;
|
|
def: shift_rotate_reg16_pat<srl, SrlvRxRy16>;
|
|
|
|
class LoadM16_pat<PatFrag OpNode, Instruction I> :
|
|
Mips16Pat<(OpNode addr16:$addr), (I addr16:$addr)>;
|
|
|
|
def: LoadM16_pat<sextloadi8, LbRxRyOffMemX16>;
|
|
def: LoadM16_pat<zextloadi8, LbuRxRyOffMemX16>;
|
|
def: LoadM16_pat<sextloadi16, LhRxRyOffMemX16>;
|
|
def: LoadM16_pat<zextloadi16, LhuRxRyOffMemX16>;
|
|
def: LoadM16_pat<load, LwRxRyOffMemX16>;
|
|
|
|
class StoreM16_pat<PatFrag OpNode, Instruction I> :
|
|
Mips16Pat<(OpNode CPU16Regs:$r, addr16:$addr),
|
|
(I CPU16Regs:$r, addr16:$addr)>;
|
|
|
|
def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
|
|
def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
|
|
def: StoreM16_pat<store, SwRxRyOffMemX16>;
|
|
|
|
// Unconditional branch
|
|
class UncondBranch16_pat<SDNode OpNode, Instruction I>:
|
|
Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
|
|
let Predicates = [InMips16Mode];
|
|
}
|
|
|
|
def : Mips16Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
|
|
(Jal16 tglobaladdr:$dst)>;
|
|
|
|
def : Mips16Pat<(MipsJmpLink (i32 texternalsym:$dst)),
|
|
(Jal16 texternalsym:$dst)>;
|
|
|
|
// Indirect branch
|
|
def: Mips16Pat<
|
|
(brind CPU16Regs:$rs),
|
|
(JrcRx16 CPU16Regs:$rs)>;
|
|
|
|
// Jump and Link (Call)
|
|
let isCall=1, hasDelaySlot=0 in
|
|
def JumpLinkReg16:
|
|
FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
|
|
"jalrc \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
|
|
|
|
// Mips16 pseudos
|
|
let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
|
|
hasExtraSrcRegAllocReq = 1 in
|
|
def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
|
|
|
|
|
|
// setcc patterns
|
|
|
|
class SetCC_R16<PatFrag cond_op, Instruction I>:
|
|
Mips16Pat<(cond_op CPU16Regs:$rx, CPU16Regs:$ry),
|
|
(I CPU16Regs:$rx, CPU16Regs:$ry)>;
|
|
|
|
class SetCC_I16<PatFrag cond_op, PatLeaf imm_type, Instruction I>:
|
|
Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16),
|
|
(I CPU16Regs:$rx, imm_type:$imm16)>;
|
|
|
|
|
|
def: Mips16Pat<(i32 addr16:$addr),
|
|
(AddiuRxRyOffMemX16 addr16:$addr)>;
|
|
|
|
|
|
// Large (>16 bit) immediate loads
|
|
def : Mips16Pat<(i32 imm:$imm), (LwConstant32 imm:$imm)>;
|
|
|
|
// Carry MipsPatterns
|
|
def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs),
|
|
(SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
|
|
def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs),
|
|
(AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
|
|
def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm),
|
|
(AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>;
|
|
|
|
//
|
|
// Some branch conditional patterns are not generated by llvm at this time.
|
|
// Some are for seemingly arbitrary reasons not used: i.e. with signed number
|
|
// comparison they are used and for unsigned a different pattern is used.
|
|
// I am pushing upstream from the full mips16 port and it seemed that I needed
|
|
// these earlier and the mips32 port has these but now I cannot create test
|
|
// cases that use these patterns. While I sort this all out I will leave these
|
|
// extra patterns commented out and if I can be sure they are really not used,
|
|
// I will delete the code. I don't want to check the code in uncommented without
|
|
// a valid test case. In some cases, the compiler is generating patterns with
|
|
// setcc instead and earlier I had implemented setcc first so may have masked
|
|
// the problem. The setcc variants are suboptimal for mips16 so I may wantto
|
|
// figure out how to enable the brcond patterns or else possibly new
|
|
// combinations of of brcond and setcc.
|
|
//
|
|
//
|
|
// bcond-seteq
|
|
//
|
|
def: Mips16Pat
|
|
<(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
|
|
(BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
|
|
>;
|
|
|
|
|
|
def: Mips16Pat
|
|
<(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
|
|
(BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
|
|
>;
|
|
|
|
def: Mips16Pat
|
|
<(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
|
|
(BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16)
|
|
>;
|
|
|
|
//
|
|
// bcond-setgt (do we need to have this pair of setlt, setgt??)
|
|
//
|
|
def: Mips16Pat
|
|
<(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
|
|
(BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
|
|
>;
|
|
|
|
//
|
|
// bcond-setge
|
|
//
|
|
def: Mips16Pat
|
|
<(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
|
|
(BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
|
|
>;
|
|
|
|
//
|
|
// never called because compiler transforms a >= k to a > (k-1)
|
|
def: Mips16Pat
|
|
<(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
|
|
(BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
|
|
>;
|
|
|
|
//
|
|
// bcond-setlt
|
|
//
|
|
def: Mips16Pat
|
|
<(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
|
|
(BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
|
|
>;
|
|
|
|
def: Mips16Pat
|
|
<(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
|
|
(BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
|
|
>;
|
|
|
|
//
|
|
// bcond-setle
|
|
//
|
|
def: Mips16Pat
|
|
<(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
|
|
(BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
|
|
>;
|
|
|
|
//
|
|
// bcond-setne
|
|
//
|
|
def: Mips16Pat
|
|
<(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
|
|
(BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
|
|
>;
|
|
|
|
def: Mips16Pat
|
|
<(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
|
|
(BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
|
|
>;
|
|
|
|
def: Mips16Pat
|
|
<(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
|
|
(BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
|
|
>;
|
|
|
|
//
|
|
// This needs to be there but I forget which code will generate it
|
|
//
|
|
def: Mips16Pat
|
|
<(brcond CPU16Regs:$rx, bb:$targ16),
|
|
(BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
|
|
>;
|
|
|
|
//
|
|
|
|
//
|
|
// bcond-setugt
|
|
//
|
|
//def: Mips16Pat
|
|
// <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
|
|
// (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
|
|
// >;
|
|
|
|
//
|
|
// bcond-setuge
|
|
//
|
|
//def: Mips16Pat
|
|
// <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
|
|
// (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
|
|
// >;
|
|
|
|
|
|
//
|
|
// bcond-setult
|
|
//
|
|
//def: Mips16Pat
|
|
// <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
|
|
// (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
|
|
// >;
|
|
|
|
def: UncondBranch16_pat<br, BimmX16>;
|
|
|
|
// Small immediates
|
|
def: Mips16Pat<(i32 immSExt16:$in),
|
|
(AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>;
|
|
|
|
def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
|
|
|
|
//
|
|
// MipsDivRem
|
|
//
|
|
def: Mips16Pat
|
|
<(MipsDivRem16 CPU16Regs:$rx, CPU16Regs:$ry),
|
|
(DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
|
|
|
|
//
|
|
// MipsDivRemU
|
|
//
|
|
def: Mips16Pat
|
|
<(MipsDivRemU16 CPU16Regs:$rx, CPU16Regs:$ry),
|
|
(DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
|
|
|
|
// signed a,b
|
|
// x = (a>=b)?x:y
|
|
//
|
|
// if !(a < b) x = y
|
|
//
|
|
def : Mips16Pat<(select (i32 (setge CPU16Regs:$a, CPU16Regs:$b)),
|
|
CPU16Regs:$x, CPU16Regs:$y),
|
|
(SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
|
|
CPU16Regs:$a, CPU16Regs:$b)>;
|
|
|
|
// signed a,b
|
|
// x = (a>b)?x:y
|
|
//
|
|
// if (b < a) x = y
|
|
//
|
|
def : Mips16Pat<(select (i32 (setgt CPU16Regs:$a, CPU16Regs:$b)),
|
|
CPU16Regs:$x, CPU16Regs:$y),
|
|
(SelTBtneZSlt CPU16Regs:$x, CPU16Regs:$y,
|
|
CPU16Regs:$b, CPU16Regs:$a)>;
|
|
|
|
// unsigned a,b
|
|
// x = (a>=b)?x:y
|
|
//
|
|
// if !(a < b) x = y;
|
|
//
|
|
def : Mips16Pat<
|
|
(select (i32 (setuge CPU16Regs:$a, CPU16Regs:$b)),
|
|
CPU16Regs:$x, CPU16Regs:$y),
|
|
(SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
|
|
CPU16Regs:$a, CPU16Regs:$b)>;
|
|
|
|
// unsigned a,b
|
|
// x = (a>b)?x:y
|
|
//
|
|
// if (b < a) x = y
|
|
//
|
|
def : Mips16Pat<(select (i32 (setugt CPU16Regs:$a, CPU16Regs:$b)),
|
|
CPU16Regs:$x, CPU16Regs:$y),
|
|
(SelTBtneZSltu CPU16Regs:$x, CPU16Regs:$y,
|
|
CPU16Regs:$b, CPU16Regs:$a)>;
|
|
|
|
// signed
|
|
// x = (a >= k)?x:y
|
|
// due to an llvm optimization, i don't think that this will ever
|
|
// be used. This is transformed into x = (a > k-1)?x:y
|
|
//
|
|
//
|
|
|
|
//def : Mips16Pat<
|
|
// (select (i32 (setge CPU16Regs:$lhs, immSExt16:$rhs)),
|
|
// CPU16Regs:$T, CPU16Regs:$F),
|
|
// (SelTBteqZSlti CPU16Regs:$T, CPU16Regs:$F,
|
|
// CPU16Regs:$lhs, immSExt16:$rhs)>;
|
|
|
|
//def : Mips16Pat<
|
|
// (select (i32 (setuge CPU16Regs:$lhs, immSExt16:$rhs)),
|
|
// CPU16Regs:$T, CPU16Regs:$F),
|
|
// (SelTBteqZSltiu CPU16Regs:$T, CPU16Regs:$F,
|
|
// CPU16Regs:$lhs, immSExt16:$rhs)>;
|
|
|
|
// signed
|
|
// x = (a < k)?x:y
|
|
//
|
|
// if !(a < k) x = y;
|
|
//
|
|
def : Mips16Pat<
|
|
(select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
|
|
CPU16Regs:$x, CPU16Regs:$y),
|
|
(SelTBtneZSlti CPU16Regs:$x, CPU16Regs:$y,
|
|
CPU16Regs:$a, immSExt16:$b)>;
|
|
|
|
|
|
//
|
|
//
|
|
// signed
|
|
// x = (a <= b)? x : y
|
|
//
|
|
// if (b < a) x = y
|
|
//
|
|
def : Mips16Pat<(select (i32 (setle CPU16Regs:$a, CPU16Regs:$b)),
|
|
CPU16Regs:$x, CPU16Regs:$y),
|
|
(SelTBteqZSlt CPU16Regs:$x, CPU16Regs:$y,
|
|
CPU16Regs:$b, CPU16Regs:$a)>;
|
|
|
|
//
|
|
// unnsigned
|
|
// x = (a <= b)? x : y
|
|
//
|
|
// if (b < a) x = y
|
|
//
|
|
def : Mips16Pat<(select (i32 (setule CPU16Regs:$a, CPU16Regs:$b)),
|
|
CPU16Regs:$x, CPU16Regs:$y),
|
|
(SelTBteqZSltu CPU16Regs:$x, CPU16Regs:$y,
|
|
CPU16Regs:$b, CPU16Regs:$a)>;
|
|
|
|
//
|
|
// signed/unsigned
|
|
// x = (a == b)? x : y
|
|
//
|
|
// if (a != b) x = y
|
|
//
|
|
def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, CPU16Regs:$b)),
|
|
CPU16Regs:$x, CPU16Regs:$y),
|
|
(SelTBteqZCmp CPU16Regs:$x, CPU16Regs:$y,
|
|
CPU16Regs:$b, CPU16Regs:$a)>;
|
|
|
|
//
|
|
// signed/unsigned
|
|
// x = (a == 0)? x : y
|
|
//
|
|
// if (a != 0) x = y
|
|
//
|
|
def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, 0)),
|
|
CPU16Regs:$x, CPU16Regs:$y),
|
|
(SelBeqZ CPU16Regs:$x, CPU16Regs:$y,
|
|
CPU16Regs:$a)>;
|
|
|
|
|
|
//
|
|
// signed/unsigned
|
|
// x = (a == k)? x : y
|
|
//
|
|
// if (a != k) x = y
|
|
//
|
|
def : Mips16Pat<(select (i32 (seteq CPU16Regs:$a, immZExt16:$k)),
|
|
CPU16Regs:$x, CPU16Regs:$y),
|
|
(SelTBteqZCmpi CPU16Regs:$x, CPU16Regs:$y,
|
|
CPU16Regs:$a, immZExt16:$k)>;
|
|
|
|
|
|
//
|
|
// signed/unsigned
|
|
// x = (a != b)? x : y
|
|
//
|
|
// if (a == b) x = y
|
|
//
|
|
//
|
|
def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, CPU16Regs:$b)),
|
|
CPU16Regs:$x, CPU16Regs:$y),
|
|
(SelTBtneZCmp CPU16Regs:$x, CPU16Regs:$y,
|
|
CPU16Regs:$b, CPU16Regs:$a)>;
|
|
|
|
//
|
|
// signed/unsigned
|
|
// x = (a != 0)? x : y
|
|
//
|
|
// if (a == 0) x = y
|
|
//
|
|
def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, 0)),
|
|
CPU16Regs:$x, CPU16Regs:$y),
|
|
(SelBneZ CPU16Regs:$x, CPU16Regs:$y,
|
|
CPU16Regs:$a)>;
|
|
|
|
// signed/unsigned
|
|
// x = (a)? x : y
|
|
//
|
|
// if (!a) x = y
|
|
//
|
|
def : Mips16Pat<(select CPU16Regs:$a,
|
|
CPU16Regs:$x, CPU16Regs:$y),
|
|
(SelBneZ CPU16Regs:$x, CPU16Regs:$y,
|
|
CPU16Regs:$a)>;
|
|
|
|
|
|
//
|
|
// signed/unsigned
|
|
// x = (a != k)? x : y
|
|
//
|
|
// if (a == k) x = y
|
|
//
|
|
def : Mips16Pat<(select (i32 (setne CPU16Regs:$a, immZExt16:$k)),
|
|
CPU16Regs:$x, CPU16Regs:$y),
|
|
(SelTBtneZCmpi CPU16Regs:$x, CPU16Regs:$y,
|
|
CPU16Regs:$a, immZExt16:$k)>;
|
|
|
|
//
|
|
// When writing C code to test setxx these patterns,
|
|
// some will be transformed into
|
|
// other things. So we test using C code but using -O3 and -O0
|
|
//
|
|
// seteq
|
|
//
|
|
def : Mips16Pat
|
|
<(seteq CPU16Regs:$lhs,CPU16Regs:$rhs),
|
|
(SltiuCCRxImmX16 (XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs), 1)>;
|
|
|
|
def : Mips16Pat
|
|
<(seteq CPU16Regs:$lhs, 0),
|
|
(SltiuCCRxImmX16 CPU16Regs:$lhs, 1)>;
|
|
|
|
|
|
//
|
|
// setge
|
|
//
|
|
|
|
def: Mips16Pat
|
|
<(setge CPU16Regs:$lhs, CPU16Regs:$rhs),
|
|
(XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
|
|
(LiRxImmX16 1))>;
|
|
|
|
//
|
|
// For constants, llvm transforms this to:
|
|
// x > (k -1) and then reverses the operands to use setlt. So this pattern
|
|
// is not used now by the compiler. (Presumably checking that k-1 does not
|
|
// overflow). The compiler never uses this at a the current time, due to
|
|
// other optimizations.
|
|
//
|
|
//def: Mips16Pat
|
|
// <(setge CPU16Regs:$lhs, immSExt16:$rhs),
|
|
// (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immSExt16:$rhs),
|
|
// (LiRxImmX16 1))>;
|
|
|
|
// This catches the x >= -32768 case by transforming it to x > -32769
|
|
//
|
|
def: Mips16Pat
|
|
<(setgt CPU16Regs:$lhs, -32769),
|
|
(XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, -32768),
|
|
(LiRxImmX16 1))>;
|
|
|
|
//
|
|
// setgt
|
|
//
|
|
//
|
|
|
|
def: Mips16Pat
|
|
<(setgt CPU16Regs:$lhs, CPU16Regs:$rhs),
|
|
(SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
|
|
|
|
//
|
|
// setle
|
|
//
|
|
def: Mips16Pat
|
|
<(setle CPU16Regs:$lhs, CPU16Regs:$rhs),
|
|
(XorRxRxRy16 (SltCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImm16 1))>;
|
|
|
|
//
|
|
// setlt
|
|
//
|
|
def: SetCC_R16<setlt, SltCCRxRy16>;
|
|
|
|
def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
|
|
|
|
//
|
|
// setne
|
|
//
|
|
def : Mips16Pat
|
|
<(setne CPU16Regs:$lhs,CPU16Regs:$rhs),
|
|
(SltuCCRxRy16 (LiRxImmX16 0),
|
|
(XorRxRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs))>;
|
|
|
|
|
|
//
|
|
// setuge
|
|
//
|
|
def: Mips16Pat
|
|
<(setuge CPU16Regs:$lhs, CPU16Regs:$rhs),
|
|
(XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$lhs, CPU16Regs:$rhs),
|
|
(LiRxImmX16 1))>;
|
|
|
|
// this pattern will never be used because the compiler will transform
|
|
// x >= k to x > (k - 1) and then use SLT
|
|
//
|
|
//def: Mips16Pat
|
|
// <(setuge CPU16Regs:$lhs, immZExt16:$rhs),
|
|
// (XorRxRxRy16 (SltiuCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs),
|
|
// (LiRxImmX16 1))>;
|
|
|
|
//
|
|
// setugt
|
|
//
|
|
def: Mips16Pat
|
|
<(setugt CPU16Regs:$lhs, CPU16Regs:$rhs),
|
|
(SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs)>;
|
|
|
|
//
|
|
// setule
|
|
//
|
|
def: Mips16Pat
|
|
<(setule CPU16Regs:$lhs, CPU16Regs:$rhs),
|
|
(XorRxRxRy16 (SltuCCRxRy16 CPU16Regs:$rhs, CPU16Regs:$lhs), (LiRxImmX16 1))>;
|
|
|
|
//
|
|
// setult
|
|
//
|
|
def: SetCC_R16<setult, SltuCCRxRy16>;
|
|
|
|
def: SetCC_I16<setult, immSExt16, SltiuCCRxImmX16>;
|
|
|
|
def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
|
|
(AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
|
|
|
|
// hi/lo relocs
|
|
def : Mips16Pat<(MipsHi tblockaddress:$in),
|
|
(SllX16 (LiRxImmX16 tblockaddress:$in), 16)>;
|
|
def : Mips16Pat<(MipsHi tglobaladdr:$in),
|
|
(SllX16 (LiRxImmX16 tglobaladdr:$in), 16)>;
|
|
def : Mips16Pat<(MipsHi tjumptable:$in),
|
|
(SllX16 (LiRxImmX16 tjumptable:$in), 16)>;
|
|
def : Mips16Pat<(MipsHi tglobaltlsaddr:$in),
|
|
(SllX16 (LiRxImmX16 tglobaltlsaddr:$in), 16)>;
|
|
|
|
def : Mips16Pat<(MipsLo tblockaddress:$in), (LiRxImmX16 tblockaddress:$in)>;
|
|
|
|
// wrapper_pic
|
|
class Wrapper16Pat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
|
|
Mips16Pat<(MipsWrapper RC:$gp, node:$in),
|
|
(ADDiuOp RC:$gp, node:$in)>;
|
|
|
|
|
|
def : Wrapper16Pat<tglobaladdr, AddiuRxRxImmX16, CPU16Regs>;
|
|
def : Wrapper16Pat<tglobaltlsaddr, AddiuRxRxImmX16, CPU16Regs>;
|
|
|
|
def : Mips16Pat<(i32 (extloadi8 addr16:$src)),
|
|
(LbuRxRyOffMemX16 addr16:$src)>;
|
|
def : Mips16Pat<(i32 (extloadi16 addr16:$src)),
|
|
(LhuRxRyOffMemX16 addr16:$src)>;
|
|
|
|
def: Mips16Pat<(trap), (Break16)>;
|
|
|
|
def : Mips16Pat<(sext_inreg CPU16Regs:$val, i8),
|
|
(SebRx16 CPU16Regs:$val)>;
|
|
|
|
def : Mips16Pat<(sext_inreg CPU16Regs:$val, i16),
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(SehRx16 CPU16Regs:$val)>;
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def GotPrologue16:
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MipsPseudo16<
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(outs CPU16Regs:$rh, CPU16Regs:$rl),
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(ins simm16:$immHi, simm16:$immLo),
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".align 2\n\tli\t$rh, $immHi\n\taddiu\t$rl, $$pc, $immLo\n ",[]> ;
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