mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
101 lines
4.2 KiB
LLVM
101 lines
4.2 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; FIXME: Check something here. Currently it seems fabs + fneg aren't
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; into 2 modifiers, although theoretically that should work.
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; FUNC-LABEL: {{^}}fneg_fabs_fadd_f64:
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, -|v{{\[[0-9]+:[0-9]+\]}}|
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define void @fneg_fabs_fadd_f64(double addrspace(1)* %out, double %x, double %y) {
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%fabs = call double @llvm.fabs.f64(double %x)
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%fsub = fsub double -0.000000e+00, %fabs
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%fadd = fadd double %y, %fsub
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store double %fadd, double addrspace(1)* %out, align 8
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ret void
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}
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define void @v_fneg_fabs_fadd_f64(double addrspace(1)* %out, double addrspace(1)* %xptr, double addrspace(1)* %yptr) {
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%x = load double, double addrspace(1)* %xptr, align 8
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%y = load double, double addrspace(1)* %xptr, align 8
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%fabs = call double @llvm.fabs.f64(double %x)
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%fsub = fsub double -0.000000e+00, %fabs
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%fadd = fadd double %y, %fsub
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store double %fadd, double addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}fneg_fabs_fmul_f64:
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; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, -|{{v\[[0-9]+:[0-9]+\]}}|
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define void @fneg_fabs_fmul_f64(double addrspace(1)* %out, double %x, double %y) {
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%fabs = call double @llvm.fabs.f64(double %x)
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%fsub = fsub double -0.000000e+00, %fabs
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%fmul = fmul double %y, %fsub
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store double %fmul, double addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}fneg_fabs_free_f64:
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define void @fneg_fabs_free_f64(double addrspace(1)* %out, i64 %in) {
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%bc = bitcast i64 %in to double
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%fabs = call double @llvm.fabs.f64(double %bc)
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%fsub = fsub double -0.000000e+00, %fabs
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store double %fsub, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fneg_fabs_fn_free_f64:
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; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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define void @fneg_fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) {
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%bc = bitcast i64 %in to double
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%fabs = call double @fabs(double %bc)
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%fsub = fsub double -0.000000e+00, %fabs
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store double %fsub, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fneg_fabs_f64:
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; SI: s_load_dwordx2 s{{\[}}[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]{{\]}}
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; SI: s_load_dwordx2
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; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI-DAG: v_or_b32_e32 v[[HI_V:[0-9]+]], s[[HI_X]], [[IMMREG]]
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; SI-DAG: v_mov_b32_e32 v[[LO_V:[0-9]+]], s[[LO_X]]
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; SI: buffer_store_dwordx2 v{{\[}}[[LO_V]]:[[HI_V]]{{\]}}
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define void @fneg_fabs_f64(double addrspace(1)* %out, double %in) {
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%fabs = call double @llvm.fabs.f64(double %in)
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%fsub = fsub double -0.000000e+00, %fabs
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store double %fsub, double addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}fneg_fabs_v2f64:
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; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI-NOT: 0x80000000
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; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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define void @fneg_fabs_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) {
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%fabs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %in)
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%fsub = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %fabs
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store <2 x double> %fsub, <2 x double> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fneg_fabs_v4f64:
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; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000
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; SI-NOT: 0x80000000
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; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]]
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define void @fneg_fabs_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) {
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%fabs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %in)
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%fsub = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %fabs
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store <4 x double> %fsub, <4 x double> addrspace(1)* %out
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ret void
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}
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declare double @fabs(double) readnone
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declare double @llvm.fabs.f64(double) readnone
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declare <2 x double> @llvm.fabs.v2f64(<2 x double>) readnone
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declare <4 x double> @llvm.fabs.v4f64(<4 x double>) readnone
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