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https://github.com/c64scene-ar/llvm-6502.git
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f98f2ce29e
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
90 lines
2.8 KiB
C++
90 lines
2.8 KiB
C++
//===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief SI Implementation of TargetInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "SIInstrInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include <stdio.h>
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using namespace llvm;
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SIInstrInfo::SIInstrInfo(AMDGPUTargetMachine &tm)
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: AMDGPUInstrInfo(tm),
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RI(tm, *this)
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{ }
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const SIRegisterInfo &SIInstrInfo::getRegisterInfo() const {
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return RI;
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}
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void
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SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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// If we are trying to copy to or from SCC, there is a bug somewhere else in
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// the backend. While it may be theoretically possible to do this, it should
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// never be necessary.
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assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC);
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if (AMDGPU::SReg_64RegClass.contains(DestReg)) {
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assert(AMDGPU::SReg_64RegClass.contains(SrcReg));
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BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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} else if (AMDGPU::VReg_32RegClass.contains(DestReg)) {
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assert(AMDGPU::VReg_32RegClass.contains(SrcReg) ||
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AMDGPU::SReg_32RegClass.contains(SrcReg));
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BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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} else {
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assert(AMDGPU::SReg_32RegClass.contains(DestReg));
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assert(AMDGPU::SReg_32RegClass.contains(SrcReg));
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BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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}
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}
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MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg,
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int64_t Imm) const {
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MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc());
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MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
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MachineInstrBuilder(MI).addImm(Imm);
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return MI;
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}
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bool SIInstrInfo::isMov(unsigned Opcode) const {
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switch(Opcode) {
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default: return false;
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case AMDGPU::S_MOV_B32:
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case AMDGPU::S_MOV_B64:
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case AMDGPU::V_MOV_B32_e32:
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case AMDGPU::V_MOV_B32_e64:
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case AMDGPU::V_MOV_IMM_F32:
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case AMDGPU::V_MOV_IMM_I32:
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case AMDGPU::S_MOV_IMM_I32:
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return true;
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}
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}
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bool
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SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
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return RC != &AMDGPU::EXECRegRegClass;
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}
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