llvm-6502/lib/Target/ARM/Disassembler
Johnny Chen ec51a6225c The Thumb2 RFE instructions need to have their second halfword fully specified.
In addition, the base register is not rGPR, but GPR with th exception that:

    if n == 15 then UNPREDICTABLE

rdar://problem/9273836


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129391 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-12 21:41:51 +00:00
..
ARMDisassembler.cpp Adding support for printing operands symbolically to llvm's public 'C' 2011-04-11 18:08:50 +00:00
ARMDisassembler.h Better error handling of invalid IT mask '0000', instead of just asserting. 2010-04-19 23:02:58 +00:00
ARMDisassemblerCore.cpp Trivial comment fix. 2011-04-11 18:51:50 +00:00
ARMDisassemblerCore.h Print out a debug message when the reglist fails the sanity check for Thumb Ld/St Multiple. 2011-04-12 17:09:04 +00:00
CMakeLists.txt CMake: Add disabling optimization on MSVC8 and MSVC10 as workaround for some files in Target/ARM and Target/X86. 2010-12-29 03:59:27 +00:00
Makefile Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call in 2010-04-07 20:53:12 +00:00
ThumbDisassemblerCore.h The Thumb2 RFE instructions need to have their second halfword fully specified. 2011-04-12 21:41:51 +00:00