Kevin Qin 10ecde5c34 [AArch64] Add register constraints to avoid generating STLXR and STXR with unpredictable behavior. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201841 91177308-0d34-0410-b5e6-96231b3b80d8		2014-02-21 07:45:48 +00:00
..
Analysis
Assembler
Bindings
Bitcode
BugPoint
CodeGen	[AArch64] Add register constraints to avoid generating STLXR and STXR with unpredictable behavior.	2014-02-21 07:45:48 +00:00
DebugInfo	Add support for hashing attributes with DW_FORM_block. This required	2014-02-20 02:50:45 +00:00
ExecutionEngine
Feature
FileCheck
Instrumentation	Add back r201608, r201622, r201624 and r201625	2014-02-19 17:23:20 +00:00
Integer
JitListener
Linker
LTO	Add back r201608, r201622, r201624 and r201625	2014-02-19 17:23:20 +00:00
MC	[mips] Make it impossible to have UnknownABI in CodeGen and Integrated Assembler.	2014-02-20 14:58:19 +00:00
Object
Other
TableGen
tools	llvm-objdump/COFF: Print SEH table addresses.	2014-02-20 06:51:07 +00:00
Transforms	Make sure that value handle users see the transformation of an indirect call to a direct call. This is important for the CallGraph iteration. Patch by Björn Steinbrink!	2014-02-20 23:00:15 +00:00
Unit
Verifier
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg
lit.site.cfg.in
Makefile
Makefile.tests
TestRunner.sh