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This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195064 91177308-0d34-0410-b5e6-96231b3b80d8
703 lines
27 KiB
C++
703 lines
27 KiB
C++
//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the MachineRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
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#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include <vector>
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namespace llvm {
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class PSetIterator;
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/// MachineRegisterInfo - Keep track of information for virtual and physical
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/// registers, including vreg register classes, use/def chains for registers,
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/// etc.
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class MachineRegisterInfo {
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public:
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class Delegate {
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virtual void anchor();
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public:
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virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
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virtual ~Delegate() {}
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};
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private:
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const TargetMachine &TM;
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Delegate *TheDelegate;
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/// IsSSA - True when the machine function is in SSA form and virtual
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/// registers have a single def.
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bool IsSSA;
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/// TracksLiveness - True while register liveness is being tracked accurately.
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/// Basic block live-in lists, kill flags, and implicit defs may not be
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/// accurate when after this flag is cleared.
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bool TracksLiveness;
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/// VRegInfo - Information we keep for each virtual register.
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///
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/// Each element in this list contains the register class of the vreg and the
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/// start of the use/def list for the register.
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IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>,
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VirtReg2IndexFunctor> VRegInfo;
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/// RegAllocHints - This vector records register allocation hints for virtual
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/// registers. For each virtual register, it keeps a register and hint type
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/// pair making up the allocation hint. Hint type is target specific except
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/// for the value 0 which means the second value of the pair is the preferred
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/// register for allocation. For example, if the hint is <0, 1024>, it means
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/// the allocator should prefer the physical register allocated to the virtual
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/// register of the hint.
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IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints;
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/// PhysRegUseDefLists - This is an array of the head of the use/def list for
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/// physical registers.
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MachineOperand **PhysRegUseDefLists;
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/// getRegUseDefListHead - Return the head pointer for the register use/def
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/// list for the specified virtual or physical register.
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MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
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if (TargetRegisterInfo::isVirtualRegister(RegNo))
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return VRegInfo[RegNo].second;
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return PhysRegUseDefLists[RegNo];
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}
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MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
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if (TargetRegisterInfo::isVirtualRegister(RegNo))
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return VRegInfo[RegNo].second;
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return PhysRegUseDefLists[RegNo];
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}
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/// Get the next element in the use-def chain.
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static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
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assert(MO && MO->isReg() && "This is not a register operand!");
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return MO->Contents.Reg.Next;
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}
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/// UsedRegUnits - This is a bit vector that is computed and set by the
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/// register allocator, and must be kept up to date by passes that run after
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/// register allocation (though most don't modify this). This is used
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/// so that the code generator knows which callee save registers to save and
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/// for other target specific uses.
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/// This vector has bits set for register units that are modified in the
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/// current function. It doesn't include registers clobbered by function
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/// calls with register mask operands.
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BitVector UsedRegUnits;
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/// UsedPhysRegMask - Additional used physregs including aliases.
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/// This bit vector represents all the registers clobbered by function calls.
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/// It can model things that UsedRegUnits can't, such as function calls that
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/// clobber ymm7 but preserve the low half in xmm7.
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BitVector UsedPhysRegMask;
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/// ReservedRegs - This is a bit vector of reserved registers. The target
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/// may change its mind about which registers should be reserved. This
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/// vector is the frozen set of reserved registers when register allocation
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/// started.
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BitVector ReservedRegs;
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/// Keep track of the physical registers that are live in to the function.
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/// Live in values are typically arguments in registers. LiveIn values are
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/// allowed to have virtual registers associated with them, stored in the
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/// second element.
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std::vector<std::pair<unsigned, unsigned> > LiveIns;
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MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
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void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
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public:
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explicit MachineRegisterInfo(const TargetMachine &TM);
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~MachineRegisterInfo();
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const TargetRegisterInfo *getTargetRegisterInfo() const {
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return TM.getRegisterInfo();
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}
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void resetDelegate(Delegate *delegate) {
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// Ensure another delegate does not take over unless the current
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// delegate first unattaches itself. If we ever need to multicast
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// notifications, we will need to change to using a list.
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assert(TheDelegate == delegate &&
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"Only the current delegate can perform reset!");
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TheDelegate = 0;
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}
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void setDelegate(Delegate *delegate) {
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assert(delegate && !TheDelegate &&
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"Attempted to set delegate to null, or to change it without "
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"first resetting it!");
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TheDelegate = delegate;
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}
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//===--------------------------------------------------------------------===//
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// Function State
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//===--------------------------------------------------------------------===//
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// isSSA - Returns true when the machine function is in SSA form. Early
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// passes require the machine function to be in SSA form where every virtual
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// register has a single defining instruction.
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//
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// The TwoAddressInstructionPass and PHIElimination passes take the machine
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// function out of SSA form when they introduce multiple defs per virtual
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// register.
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bool isSSA() const { return IsSSA; }
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// leaveSSA - Indicates that the machine function is no longer in SSA form.
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void leaveSSA() { IsSSA = false; }
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/// tracksLiveness - Returns true when tracking register liveness accurately.
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///
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/// While this flag is true, register liveness information in basic block
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/// live-in lists and machine instruction operands is accurate. This means it
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/// can be used to change the code in ways that affect the values in
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/// registers, for example by the register scavenger.
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///
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/// When this flag is false, liveness is no longer reliable.
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bool tracksLiveness() const { return TracksLiveness; }
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/// invalidateLiveness - Indicates that register liveness is no longer being
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/// tracked accurately.
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///
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/// This should be called by late passes that invalidate the liveness
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/// information.
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void invalidateLiveness() { TracksLiveness = false; }
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//===--------------------------------------------------------------------===//
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// Register Info
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//===--------------------------------------------------------------------===//
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// Strictly for use by MachineInstr.cpp.
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void addRegOperandToUseList(MachineOperand *MO);
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// Strictly for use by MachineInstr.cpp.
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void removeRegOperandFromUseList(MachineOperand *MO);
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// Strictly for use by MachineInstr.cpp.
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void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
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/// Verify the sanity of the use list for Reg.
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void verifyUseList(unsigned Reg) const;
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/// Verify the use list of all registers.
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void verifyUseLists() const;
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/// reg_begin/reg_end - Provide iteration support to walk over all definitions
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/// and uses of a register within the MachineFunction that corresponds to this
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/// MachineRegisterInfo object.
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template<bool Uses, bool Defs, bool SkipDebug>
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class defusechain_iterator;
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// Make it a friend so it can access getNextOperandForReg().
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template<bool, bool, bool> friend class defusechain_iterator;
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/// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
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/// register.
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typedef defusechain_iterator<true,true,false> reg_iterator;
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reg_iterator reg_begin(unsigned RegNo) const {
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return reg_iterator(getRegUseDefListHead(RegNo));
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}
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static reg_iterator reg_end() { return reg_iterator(0); }
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/// reg_empty - Return true if there are no instructions using or defining the
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/// specified register (it may be live-in).
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bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
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/// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
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/// of the specified register, skipping those marked as Debug.
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typedef defusechain_iterator<true,true,true> reg_nodbg_iterator;
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reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
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return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
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}
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static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); }
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/// reg_nodbg_empty - Return true if the only instructions using or defining
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/// Reg are Debug instructions.
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bool reg_nodbg_empty(unsigned RegNo) const {
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return reg_nodbg_begin(RegNo) == reg_nodbg_end();
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}
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/// def_iterator/def_begin/def_end - Walk all defs of the specified register.
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typedef defusechain_iterator<false,true,false> def_iterator;
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def_iterator def_begin(unsigned RegNo) const {
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return def_iterator(getRegUseDefListHead(RegNo));
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}
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static def_iterator def_end() { return def_iterator(0); }
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/// def_empty - Return true if there are no instructions defining the
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/// specified register (it may be live-in).
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bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
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/// hasOneDef - Return true if there is exactly one instruction defining the
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/// specified register.
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bool hasOneDef(unsigned RegNo) const {
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def_iterator DI = def_begin(RegNo);
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if (DI == def_end())
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return false;
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return ++DI == def_end();
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}
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/// use_iterator/use_begin/use_end - Walk all uses of the specified register.
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typedef defusechain_iterator<true,false,false> use_iterator;
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use_iterator use_begin(unsigned RegNo) const {
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return use_iterator(getRegUseDefListHead(RegNo));
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}
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static use_iterator use_end() { return use_iterator(0); }
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/// use_empty - Return true if there are no instructions using the specified
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/// register.
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bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
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/// hasOneUse - Return true if there is exactly one instruction using the
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/// specified register.
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bool hasOneUse(unsigned RegNo) const {
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use_iterator UI = use_begin(RegNo);
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if (UI == use_end())
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return false;
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return ++UI == use_end();
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}
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/// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
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/// specified register, skipping those marked as Debug.
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typedef defusechain_iterator<true,false,true> use_nodbg_iterator;
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use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
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return use_nodbg_iterator(getRegUseDefListHead(RegNo));
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}
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static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); }
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/// use_nodbg_empty - Return true if there are no non-Debug instructions
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/// using the specified register.
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bool use_nodbg_empty(unsigned RegNo) const {
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return use_nodbg_begin(RegNo) == use_nodbg_end();
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}
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/// hasOneNonDBGUse - Return true if there is exactly one non-Debug
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/// instruction using the specified register.
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bool hasOneNonDBGUse(unsigned RegNo) const;
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/// replaceRegWith - Replace all instances of FromReg with ToReg in the
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/// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
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/// except that it also changes any definitions of the register as well.
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///
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/// Note that it is usually necessary to first constrain ToReg's register
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/// class to match the FromReg constraints using:
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///
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/// constrainRegClass(ToReg, getRegClass(FromReg))
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///
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/// That function will return NULL if the virtual registers have incompatible
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/// constraints.
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void replaceRegWith(unsigned FromReg, unsigned ToReg);
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/// getVRegDef - Return the machine instr that defines the specified virtual
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/// register or null if none is found. This assumes that the code is in SSA
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/// form, so there should only be one definition.
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MachineInstr *getVRegDef(unsigned Reg) const;
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/// getUniqueVRegDef - Return the unique machine instr that defines the
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/// specified virtual register or null if none is found. If there are
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/// multiple definitions or no definition, return null.
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MachineInstr *getUniqueVRegDef(unsigned Reg) const;
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/// clearKillFlags - Iterate over all the uses of the given register and
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/// clear the kill flag from the MachineOperand. This function is used by
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/// optimization passes which extend register lifetimes and need only
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/// preserve conservative kill flag information.
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void clearKillFlags(unsigned Reg) const;
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#ifndef NDEBUG
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void dumpUses(unsigned RegNo) const;
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#endif
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/// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
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/// throughout the function. It is safe to move instructions that read such
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/// a physreg.
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bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
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/// Get an iterator over the pressure sets affected by the given physical or
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/// virtual register. If RegUnit is physical, it must be a register unit (from
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/// MCRegUnitIterator).
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PSetIterator getPressureSets(unsigned RegUnit) const;
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//===--------------------------------------------------------------------===//
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// Virtual Register Info
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//===--------------------------------------------------------------------===//
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/// getRegClass - Return the register class of the specified virtual register.
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///
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const TargetRegisterClass *getRegClass(unsigned Reg) const {
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return VRegInfo[Reg].first;
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}
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/// setRegClass - Set the register class of the specified virtual register.
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///
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void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
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/// constrainRegClass - Constrain the register class of the specified virtual
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/// register to be a common subclass of RC and the current register class,
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/// but only if the new class has at least MinNumRegs registers. Return the
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/// new register class, or NULL if no such class exists.
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/// This should only be used when the constraint is known to be trivial, like
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/// GR32 -> GR32_NOSP. Beware of increasing register pressure.
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///
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const TargetRegisterClass *constrainRegClass(unsigned Reg,
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const TargetRegisterClass *RC,
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unsigned MinNumRegs = 0);
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/// recomputeRegClass - Try to find a legal super-class of Reg's register
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/// class that still satisfies the constraints from the instructions using
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/// Reg. Returns true if Reg was upgraded.
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///
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/// This method can be used after constraints have been removed from a
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/// virtual register, for example after removing instructions or splitting
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/// the live range.
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///
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bool recomputeRegClass(unsigned Reg, const TargetMachine&);
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/// createVirtualRegister - Create and return a new virtual register in the
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/// function with the specified register class.
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///
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unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
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/// getNumVirtRegs - Return the number of virtual registers created.
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///
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unsigned getNumVirtRegs() const { return VRegInfo.size(); }
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/// clearVirtRegs - Remove all virtual registers (after physreg assignment).
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void clearVirtRegs();
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/// setRegAllocationHint - Specify a register allocation hint for the
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/// specified virtual register.
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void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
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RegAllocHints[Reg].first = Type;
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RegAllocHints[Reg].second = PrefReg;
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}
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/// getRegAllocationHint - Return the register allocation hint for the
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/// specified virtual register.
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std::pair<unsigned, unsigned>
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getRegAllocationHint(unsigned Reg) const {
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return RegAllocHints[Reg];
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}
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/// getSimpleHint - Return the preferred register allocation hint, or 0 if a
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/// standard simple hint (Type == 0) is not set.
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unsigned getSimpleHint(unsigned Reg) const {
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std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg);
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return Hint.first ? 0 : Hint.second;
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}
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//===--------------------------------------------------------------------===//
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// Physical Register Use Info
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//===--------------------------------------------------------------------===//
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/// isPhysRegUsed - Return true if the specified register is used in this
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/// function. Also check for clobbered aliases and registers clobbered by
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/// function calls with register mask operands.
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///
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/// This only works after register allocation. It is primarily used by
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/// PrologEpilogInserter to determine which callee-saved registers need
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/// spilling.
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bool isPhysRegUsed(unsigned Reg) const {
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if (UsedPhysRegMask.test(Reg))
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return true;
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for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
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Units.isValid(); ++Units)
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if (UsedRegUnits.test(*Units))
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return true;
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return false;
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}
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/// Mark the specified register unit as used in this function.
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/// This should only be called during and after register allocation.
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void setRegUnitUsed(unsigned RegUnit) {
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UsedRegUnits.set(RegUnit);
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}
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/// setPhysRegUsed - Mark the specified register used in this function.
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/// This should only be called during and after register allocation.
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void setPhysRegUsed(unsigned Reg) {
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for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
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Units.isValid(); ++Units)
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UsedRegUnits.set(*Units);
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}
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/// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
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/// This corresponds to the bit mask attached to register mask operands.
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void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
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UsedPhysRegMask.setBitsNotInMask(RegMask);
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}
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/// setPhysRegUnused - Mark the specified register unused in this function.
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/// This should only be called during and after register allocation.
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void setPhysRegUnused(unsigned Reg) {
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UsedPhysRegMask.reset(Reg);
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for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
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Units.isValid(); ++Units)
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UsedRegUnits.reset(*Units);
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}
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//===--------------------------------------------------------------------===//
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// Reserved Register Info
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//===--------------------------------------------------------------------===//
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//
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// The set of reserved registers must be invariant during register
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// allocation. For example, the target cannot suddenly decide it needs a
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// frame pointer when the register allocator has already used the frame
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// pointer register for something else.
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//
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// These methods can be used by target hooks like hasFP() to avoid changing
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// the reserved register set during register allocation.
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/// freezeReservedRegs - Called by the register allocator to freeze the set
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/// of reserved registers before allocation begins.
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void freezeReservedRegs(const MachineFunction&);
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/// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
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/// to ensure the set of reserved registers stays constant.
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bool reservedRegsFrozen() const {
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return !ReservedRegs.empty();
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}
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/// canReserveReg - Returns true if PhysReg can be used as a reserved
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/// register. Any register can be reserved before freezeReservedRegs() is
|
|
/// called.
|
|
bool canReserveReg(unsigned PhysReg) const {
|
|
return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
|
|
}
|
|
|
|
/// getReservedRegs - Returns a reference to the frozen set of reserved
|
|
/// registers. This method should always be preferred to calling
|
|
/// TRI::getReservedRegs() when possible.
|
|
const BitVector &getReservedRegs() const {
|
|
assert(reservedRegsFrozen() &&
|
|
"Reserved registers haven't been frozen yet. "
|
|
"Use TRI::getReservedRegs().");
|
|
return ReservedRegs;
|
|
}
|
|
|
|
/// isReserved - Returns true when PhysReg is a reserved register.
|
|
///
|
|
/// Reserved registers may belong to an allocatable register class, but the
|
|
/// target has explicitly requested that they are not used.
|
|
///
|
|
bool isReserved(unsigned PhysReg) const {
|
|
return getReservedRegs().test(PhysReg);
|
|
}
|
|
|
|
/// isAllocatable - Returns true when PhysReg belongs to an allocatable
|
|
/// register class and it hasn't been reserved.
|
|
///
|
|
/// Allocatable registers may show up in the allocation order of some virtual
|
|
/// register, so a register allocator needs to track its liveness and
|
|
/// availability.
|
|
bool isAllocatable(unsigned PhysReg) const {
|
|
return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
|
|
!isReserved(PhysReg);
|
|
}
|
|
|
|
//===--------------------------------------------------------------------===//
|
|
// LiveIn Management
|
|
//===--------------------------------------------------------------------===//
|
|
|
|
/// addLiveIn - Add the specified register as a live-in. Note that it
|
|
/// is an error to add the same register to the same set more than once.
|
|
void addLiveIn(unsigned Reg, unsigned vreg = 0) {
|
|
LiveIns.push_back(std::make_pair(Reg, vreg));
|
|
}
|
|
|
|
// Iteration support for the live-ins set. It's kept in sorted order
|
|
// by register number.
|
|
typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
|
|
livein_iterator;
|
|
livein_iterator livein_begin() const { return LiveIns.begin(); }
|
|
livein_iterator livein_end() const { return LiveIns.end(); }
|
|
bool livein_empty() const { return LiveIns.empty(); }
|
|
|
|
bool isLiveIn(unsigned Reg) const;
|
|
|
|
/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
|
|
/// corresponding live-in physical register.
|
|
unsigned getLiveInPhysReg(unsigned VReg) const;
|
|
|
|
/// getLiveInVirtReg - If PReg is a live-in physical register, return the
|
|
/// corresponding live-in physical register.
|
|
unsigned getLiveInVirtReg(unsigned PReg) const;
|
|
|
|
/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
|
|
/// into the given entry block.
|
|
void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
|
|
const TargetRegisterInfo &TRI,
|
|
const TargetInstrInfo &TII);
|
|
|
|
/// defusechain_iterator - This class provides iterator support for machine
|
|
/// operands in the function that use or define a specific register. If
|
|
/// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
|
|
/// returns defs. If neither are true then you are silly and it always
|
|
/// returns end(). If SkipDebug is true it skips uses marked Debug
|
|
/// when incrementing.
|
|
template<bool ReturnUses, bool ReturnDefs, bool SkipDebug>
|
|
class defusechain_iterator
|
|
: public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
|
|
MachineOperand *Op;
|
|
explicit defusechain_iterator(MachineOperand *op) : Op(op) {
|
|
// If the first node isn't one we're interested in, advance to one that
|
|
// we are interested in.
|
|
if (op) {
|
|
if ((!ReturnUses && op->isUse()) ||
|
|
(!ReturnDefs && op->isDef()) ||
|
|
(SkipDebug && op->isDebug()))
|
|
++*this;
|
|
}
|
|
}
|
|
friend class MachineRegisterInfo;
|
|
public:
|
|
typedef std::iterator<std::forward_iterator_tag,
|
|
MachineInstr, ptrdiff_t>::reference reference;
|
|
typedef std::iterator<std::forward_iterator_tag,
|
|
MachineInstr, ptrdiff_t>::pointer pointer;
|
|
|
|
defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
|
|
defusechain_iterator() : Op(0) {}
|
|
|
|
bool operator==(const defusechain_iterator &x) const {
|
|
return Op == x.Op;
|
|
}
|
|
bool operator!=(const defusechain_iterator &x) const {
|
|
return !operator==(x);
|
|
}
|
|
|
|
/// atEnd - return true if this iterator is equal to reg_end() on the value.
|
|
bool atEnd() const { return Op == 0; }
|
|
|
|
// Iterator traversal: forward iteration only
|
|
defusechain_iterator &operator++() { // Preincrement
|
|
assert(Op && "Cannot increment end iterator!");
|
|
Op = getNextOperandForReg(Op);
|
|
|
|
// All defs come before the uses, so stop def_iterator early.
|
|
if (!ReturnUses) {
|
|
if (Op) {
|
|
if (Op->isUse())
|
|
Op = 0;
|
|
else
|
|
assert(!Op->isDebug() && "Can't have debug defs");
|
|
}
|
|
} else {
|
|
// If this is an operand we don't care about, skip it.
|
|
while (Op && ((!ReturnDefs && Op->isDef()) ||
|
|
(SkipDebug && Op->isDebug())))
|
|
Op = getNextOperandForReg(Op);
|
|
}
|
|
|
|
return *this;
|
|
}
|
|
defusechain_iterator operator++(int) { // Postincrement
|
|
defusechain_iterator tmp = *this; ++*this; return tmp;
|
|
}
|
|
|
|
/// skipInstruction - move forward until reaching a different instruction.
|
|
/// Return the skipped instruction that is no longer pointed to, or NULL if
|
|
/// already pointing to end().
|
|
MachineInstr *skipInstruction() {
|
|
if (!Op) return 0;
|
|
MachineInstr *MI = Op->getParent();
|
|
do ++*this;
|
|
while (Op && Op->getParent() == MI);
|
|
return MI;
|
|
}
|
|
|
|
MachineInstr *skipBundle() {
|
|
if (!Op) return 0;
|
|
MachineInstr *MI = getBundleStart(Op->getParent());
|
|
do ++*this;
|
|
while (Op && getBundleStart(Op->getParent()) == MI);
|
|
return MI;
|
|
}
|
|
|
|
MachineOperand &getOperand() const {
|
|
assert(Op && "Cannot dereference end iterator!");
|
|
return *Op;
|
|
}
|
|
|
|
/// getOperandNo - Return the operand # of this MachineOperand in its
|
|
/// MachineInstr.
|
|
unsigned getOperandNo() const {
|
|
assert(Op && "Cannot dereference end iterator!");
|
|
return Op - &Op->getParent()->getOperand(0);
|
|
}
|
|
|
|
// Retrieve a reference to the current operand.
|
|
MachineInstr &operator*() const {
|
|
assert(Op && "Cannot dereference end iterator!");
|
|
return *Op->getParent();
|
|
}
|
|
|
|
MachineInstr *operator->() const {
|
|
assert(Op && "Cannot dereference end iterator!");
|
|
return Op->getParent();
|
|
}
|
|
};
|
|
};
|
|
|
|
/// Iterate over the pressure sets affected by the given physical or virtual
|
|
/// register. If Reg is physical, it must be a register unit (from
|
|
/// MCRegUnitIterator).
|
|
class PSetIterator {
|
|
const int *PSet;
|
|
unsigned Weight;
|
|
public:
|
|
PSetIterator(): PSet(0), Weight(0) {}
|
|
PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
|
|
const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
|
|
if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
|
|
const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
|
|
PSet = TRI->getRegClassPressureSets(RC);
|
|
Weight = TRI->getRegClassWeight(RC).RegWeight;
|
|
}
|
|
else {
|
|
PSet = TRI->getRegUnitPressureSets(RegUnit);
|
|
Weight = TRI->getRegUnitWeight(RegUnit);
|
|
}
|
|
if (*PSet == -1)
|
|
PSet = 0;
|
|
}
|
|
bool isValid() const { return PSet; }
|
|
|
|
unsigned getWeight() const { return Weight; }
|
|
|
|
unsigned operator*() const { return *PSet; }
|
|
|
|
void operator++() {
|
|
assert(isValid() && "Invalid PSetIterator.");
|
|
++PSet;
|
|
if (*PSet == -1)
|
|
PSet = 0;
|
|
}
|
|
};
|
|
|
|
inline PSetIterator MachineRegisterInfo::
|
|
getPressureSets(unsigned RegUnit) const {
|
|
return PSetIterator(RegUnit, this);
|
|
}
|
|
|
|
} // End llvm namespace
|
|
|
|
#endif
|