mirror of
https://github.com/c64scene-ar/llvm-6502.git
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59a5e979b5
This enables very common cases to switch to the smaller encoding. All of the standard LLVM canonicalizations of comparisons are the opposite of what we want. Compares with constants are moved to the RHS, but the first operand can be an inline immediate, literal constant, or SGPR using the 32-bit VOPC encoding. There are additional bad canonicalizations that should also be fixed, such as canonicalizing ge x, k to gt x, (k + 1) if this makes k no longer an inline immediate value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232988 91177308-0d34-0410-b5e6-96231b3b80d8
174 lines
5.7 KiB
LLVM
174 lines
5.7 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; FUNC-LABEL: {{^}}xor_v2i32:
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; EG: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: v_xor_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_xor_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @xor_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1) {
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%a = load <2 x i32>, <2 x i32> addrspace(1) * %in0
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%b = load <2 x i32>, <2 x i32> addrspace(1) * %in1
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%result = xor <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}xor_v4i32:
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; EG: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: v_xor_b32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_xor_b32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_xor_b32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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; SI: v_xor_b32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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define void @xor_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1) {
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%a = load <4 x i32>, <4 x i32> addrspace(1) * %in0
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%b = load <4 x i32>, <4 x i32> addrspace(1) * %in1
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%result = xor <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}xor_i1:
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; EG: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], PS}}
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; SI-DAG: v_cmp_le_f32_e32 [[CMP0:vcc]], 0, {{v[0-9]+}}
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; SI-DAG: v_cmp_le_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], 1.0, {{v[0-9]+}}
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; SI: s_xor_b64 [[XOR:s\[[0-9]+:[0-9]+\]]], [[CMP0]], [[CMP1]]
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; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, [[XOR]]
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; SI: buffer_store_dword [[RESULT]]
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; SI: s_endpgm
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define void @xor_i1(float addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) {
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%a = load float, float addrspace(1) * %in0
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%b = load float, float addrspace(1) * %in1
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%acmp = fcmp oge float %a, 0.000000e+00
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%bcmp = fcmp oge float %b, 1.000000e+00
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%xor = xor i1 %acmp, %bcmp
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%result = select i1 %xor, float %a, float %b
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store float %result, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_xor_i1:
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; SI: buffer_load_ubyte [[B:v[0-9]+]]
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; SI: buffer_load_ubyte [[A:v[0-9]+]]
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; SI: v_xor_b32_e32 [[XOR:v[0-9]+]], [[A]], [[B]]
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; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[XOR]]
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; SI: buffer_store_byte [[RESULT]]
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define void @v_xor_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in0, i1 addrspace(1)* %in1) {
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%a = load i1, i1 addrspace(1)* %in0
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%b = load i1, i1 addrspace(1)* %in1
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%xor = xor i1 %a, %b
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store i1 %xor, i1 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}vector_xor_i32:
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; SI: v_xor_b32_e32
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define void @vector_xor_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) {
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%a = load i32, i32 addrspace(1)* %in0
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%b = load i32, i32 addrspace(1)* %in1
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%result = xor i32 %a, %b
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_xor_i32:
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; SI: s_xor_b32
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define void @scalar_xor_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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%result = xor i32 %a, %b
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_not_i32:
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; SI: s_not_b32
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define void @scalar_not_i32(i32 addrspace(1)* %out, i32 %a) {
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%result = xor i32 %a, -1
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}vector_not_i32:
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; SI: v_not_b32
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define void @vector_not_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in0, i32 addrspace(1)* %in1) {
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%a = load i32, i32 addrspace(1)* %in0
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%b = load i32, i32 addrspace(1)* %in1
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%result = xor i32 %a, -1
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}vector_xor_i64:
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; SI: v_xor_b32_e32
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; SI: v_xor_b32_e32
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; SI: s_endpgm
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define void @vector_xor_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i64 addrspace(1)* %in1) {
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%a = load i64, i64 addrspace(1)* %in0
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%b = load i64, i64 addrspace(1)* %in1
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%result = xor i64 %a, %b
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_xor_i64:
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; SI: s_xor_b64
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; SI: s_endpgm
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define void @scalar_xor_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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%result = xor i64 %a, %b
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}scalar_not_i64:
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; SI: s_not_b64
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define void @scalar_not_i64(i64 addrspace(1)* %out, i64 %a) {
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%result = xor i64 %a, -1
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}vector_not_i64:
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; SI: v_not_b32
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; SI: v_not_b32
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define void @vector_not_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i64 addrspace(1)* %in1) {
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%a = load i64, i64 addrspace(1)* %in0
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%b = load i64, i64 addrspace(1)* %in1
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%result = xor i64 %a, -1
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; Test that we have a pattern to match xor inside a branch.
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; Note that in the future the backend may be smart enough to
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; use an SALU instruction for this.
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; FUNC-LABEL: {{^}}xor_cf:
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; SI: s_xor_b64
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define void @xor_cf(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b) {
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entry:
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%0 = icmp eq i64 %a, 0
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br i1 %0, label %if, label %else
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if:
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%1 = xor i64 %a, %b
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br label %endif
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else:
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%2 = load i64, i64 addrspace(1)* %in
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br label %endif
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endif:
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%3 = phi i64 [%1, %if], [%2, %else]
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store i64 %3, i64 addrspace(1)* %out
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ret void
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}
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