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https://github.com/c64scene-ar/llvm-6502.git
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d410eaba04
test suite failures. The failures occur at each stage, and only get worse, so I'm reverting all of them. Please resubmit these patches, one at a time, after verifying that the regression test suite passes. Never submit a patch without running the regression test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155372 91177308-0d34-0410-b5e6-96231b3b80d8
94 lines
3.1 KiB
C++
94 lines
3.1 KiB
C++
//===- HexagonMCInstLower.cpp - Convert Hexagon MachineInstr to an MCInst -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains code to lower Hexagon MachineInstrs to their corresponding
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// MCInst records.
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//
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//===----------------------------------------------------------------------===//
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#include "Hexagon.h"
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#include "HexagonAsmPrinter.h"
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#include "HexagonMachineFunctionInfo.h"
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#include "llvm/Constants.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Target/Mangler.h"
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using namespace llvm;
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static MCOperand GetSymbolRef(const MachineOperand& MO, const MCSymbol* Symbol,
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HexagonAsmPrinter& Printer) {
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MCContext &MC = Printer.OutContext;
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const MCExpr *ME;
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ME = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, MC);
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if (!MO.isJTI() && MO.getOffset())
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ME = MCBinaryExpr::CreateAdd(ME, MCConstantExpr::Create(MO.getOffset(), MC),
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MC);
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return (MCOperand::CreateExpr(ME));
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}
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// Create an MCInst from a MachineInstr
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void llvm::HexagonLowerToMC(const MachineInstr* MI, MCInst& MCI,
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HexagonAsmPrinter& AP) {
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MCI.setOpcode(MI->getOpcode());
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for (unsigned i = 0, e = MI->getNumOperands(); i < e; i++) {
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const MachineOperand &MO = MI->getOperand(i);
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MCOperand MCO;
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switch (MO.getType()) {
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default:
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MI->dump();
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assert(0 && "unknown operand type");
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case MachineOperand::MO_Register:
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// Ignore all implicit register operands.
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if (MO.isImplicit()) continue;
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MCO = MCOperand::CreateReg(MO.getReg());
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break;
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case MachineOperand::MO_FPImmediate: {
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APFloat Val = MO.getFPImm()->getValueAPF();
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// FP immediates are used only when setting GPRs, so they may be dealt
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// with like regular immediates from this point on.
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MCO = MCOperand::CreateImm(*Val.bitcastToAPInt().getRawData());
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break;
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}
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case MachineOperand::MO_Immediate:
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MCO = MCOperand::CreateImm(MO.getImm());
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break;
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case MachineOperand::MO_MachineBasicBlock:
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MCO = MCOperand::CreateExpr
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(MCSymbolRefExpr::Create(MO.getMBB()->getSymbol(),
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AP.OutContext));
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break;
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case MachineOperand::MO_GlobalAddress:
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MCO = GetSymbolRef(MO, AP.Mang->getSymbol(MO.getGlobal()), AP);
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break;
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case MachineOperand::MO_ExternalSymbol:
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MCO = GetSymbolRef(MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()),
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AP);
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break;
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case MachineOperand::MO_JumpTableIndex:
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MCO = GetSymbolRef(MO, AP.GetJTISymbol(MO.getIndex()), AP);
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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MCO = GetSymbolRef(MO, AP.GetCPISymbol(MO.getIndex()), AP);
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break;
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case MachineOperand::MO_BlockAddress:
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MCO = GetSymbolRef(MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()),AP);
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break;
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}
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MCI.addOperand(MCO);
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}
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}
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