mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
e06bec47d6
Summary: Previously, attempting to extract lanes 2 and 3 would actually extract lane 1. The MSA CodeGen tests only covered lanes 0 and 1. Differential Revision: http://llvm-reviews.chandlerc.com/D2935 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202848 91177308-0d34-0410-b5e6-96231b3b80d8
235 lines
6.9 KiB
LLVM
235 lines
6.9 KiB
LLVM
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
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; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32 %s
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@v4f32 = global <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>
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@v2f64 = global <2 x double> <double 0.0, double 0.0>
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@f32 = global float 0.0
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@f64 = global double 0.0
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define void @const_v4f32() nounwind {
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; MIPS32: const_v4f32:
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store volatile <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>, <4 x float>*@v4f32
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; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0
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store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float>*@v4f32
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; MIPS32: lui [[R1:\$[0-9]+]], 16256
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; MIPS32: fill.w [[R2:\$w[0-9]+]], [[R1]]
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store volatile <4 x float> <float 1.0, float 1.0, float 1.0, float 31.0>, <4 x float>*@v4f32
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; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
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; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
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store volatile <4 x float> <float 65537.0, float 65537.0, float 65537.0, float 65537.0>, <4 x float>*@v4f32
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; MIPS32: lui [[R1:\$[0-9]+]], 18304
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; MIPS32: ori [[R2:\$[0-9]+]], [[R1]], 128
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; MIPS32: fill.w [[R3:\$w[0-9]+]], [[R2]]
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store volatile <4 x float> <float 1.0, float 2.0, float 1.0, float 2.0>, <4 x float>*@v4f32
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; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
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; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
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store volatile <4 x float> <float 3.0, float 4.0, float 5.0, float 6.0>, <4 x float>*@v4f32
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; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
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; MIPS32: ld.w [[R1:\$w[0-9]+]], 0([[G_PTR]])
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ret void
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; MIPS32: .size const_v4f32
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}
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define void @const_v2f64() nounwind {
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; MIPS32: const_v2f64:
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store volatile <2 x double> <double 0.0, double 0.0>, <2 x double>*@v2f64
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; MIPS32: ldi.b [[R1:\$w[0-9]+]], 0
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store volatile <2 x double> <double 72340172838076673.0, double 72340172838076673.0>, <2 x double>*@v2f64
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; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
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; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
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store volatile <2 x double> <double 281479271743489.0, double 281479271743489.0>, <2 x double>*@v2f64
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; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
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; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
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store volatile <2 x double> <double 4294967297.0, double 4294967297.0>, <2 x double>*@v2f64
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; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
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; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
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store volatile <2 x double> <double 1.0, double 1.0>, <2 x double>*@v2f64
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; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
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; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
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store volatile <2 x double> <double 1.0, double 31.0>, <2 x double>*@v2f64
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; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
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; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
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store volatile <2 x double> <double 3.0, double 4.0>, <2 x double>*@v2f64
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; MIPS32: addiu [[G_PTR:\$[0-9]+]], {{.*}}, %lo($
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; MIPS32: ld.d [[R1:\$w[0-9]+]], 0([[G_PTR]])
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ret void
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; MIPS32: .size const_v2f64
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}
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define void @nonconst_v4f32() nounwind {
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; MIPS32: nonconst_v4f32:
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%1 = load float *@f32
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%2 = insertelement <4 x float> undef, float %1, i32 0
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%3 = insertelement <4 x float> %2, float %1, i32 1
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%4 = insertelement <4 x float> %3, float %1, i32 2
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%5 = insertelement <4 x float> %4, float %1, i32 3
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store volatile <4 x float> %5, <4 x float>*@v4f32
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; MIPS32: lwc1 $f[[R1:[0-9]+]], 0(
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; MIPS32: splati.w [[R2:\$w[0-9]+]], $w[[R1]]
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ret void
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; MIPS32: .size nonconst_v4f32
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}
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define void @nonconst_v2f64() nounwind {
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; MIPS32: nonconst_v2f64:
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%1 = load double *@f64
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%2 = insertelement <2 x double> undef, double %1, i32 0
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%3 = insertelement <2 x double> %2, double %1, i32 1
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store volatile <2 x double> %3, <2 x double>*@v2f64
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; MIPS32: ldc1 $f[[R1:[0-9]+]], 0(
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; MIPS32: splati.d [[R2:\$w[0-9]+]], $w[[R1]]
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ret void
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; MIPS32: .size nonconst_v2f64
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}
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define float @extract_v4f32() nounwind {
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; MIPS32: extract_v4f32:
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%1 = load <4 x float>* @v4f32
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; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
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%2 = fadd <4 x float> %1, %1
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; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
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%3 = extractelement <4 x float> %2, i32 1
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; Element 1 can be obtained by splatting it across the vector and extracting
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; $w0:sub_lo
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; MIPS32-DAG: splati.w $w0, [[R1]][1]
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ret float %3
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; MIPS32: .size extract_v4f32
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}
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define float @extract_v4f32_elt0() nounwind {
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; MIPS32: extract_v4f32_elt0:
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%1 = load <4 x float>* @v4f32
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; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
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%2 = fadd <4 x float> %1, %1
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; MIPS32-DAG: fadd.w $w0, [[R1]], [[R1]]
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%3 = extractelement <4 x float> %2, i32 0
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; Element 0 can be obtained by extracting $w0:sub_lo ($f0)
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; MIPS32-NOT: copy_u.w
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; MIPS32-NOT: mtc1
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ret float %3
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; MIPS32: .size extract_v4f32_elt0
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}
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define float @extract_v4f32_elt2() nounwind {
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; MIPS32: extract_v4f32_elt2:
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%1 = load <4 x float>* @v4f32
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; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
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%2 = fadd <4 x float> %1, %1
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; MIPS32-DAG: fadd.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
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%3 = extractelement <4 x float> %2, i32 2
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; Element 2 can be obtained by splatting it across the vector and extracting
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; $w0:sub_lo
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; MIPS32-DAG: splati.w $w0, [[R1]][2]
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ret float %3
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; MIPS32: .size extract_v4f32_elt2
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}
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define double @extract_v2f64() nounwind {
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; MIPS32: extract_v2f64:
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%1 = load <2 x double>* @v2f64
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; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
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%2 = fadd <2 x double> %1, %1
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; MIPS32-DAG: fadd.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
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%3 = extractelement <2 x double> %2, i32 1
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; Element 1 can be obtained by splatting it across the vector and extracting
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; $w0:sub_64
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; MIPS32-DAG: splati.d $w0, [[R1]][1]
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; MIPS32-NOT: copy_u.w
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; MIPS32-NOT: mtc1
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; MIPS32-NOT: mthc1
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; MIPS32-NOT: sll
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; MIPS32-NOT: sra
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ret double %3
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; MIPS32: .size extract_v2f64
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}
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define double @extract_v2f64_elt0() nounwind {
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; MIPS32: extract_v2f64_elt0:
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%1 = load <2 x double>* @v2f64
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; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
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%2 = fadd <2 x double> %1, %1
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; MIPS32-DAG: fadd.d $w0, [[R1]], [[R1]]
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%3 = extractelement <2 x double> %2, i32 0
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; Element 0 can be obtained by extracting $w0:sub_64 ($f0)
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; MIPS32-NOT: copy_u.w
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; MIPS32-NOT: mtc1
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; MIPS32-NOT: mthc1
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; MIPS32-NOT: sll
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; MIPS32-NOT: sra
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ret double %3
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; MIPS32: .size extract_v2f64_elt0
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}
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define void @insert_v4f32(float %a) nounwind {
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; MIPS32: insert_v4f32:
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%1 = load <4 x float>* @v4f32
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; MIPS32-DAG: ld.w [[R1:\$w[0-9]+]],
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%2 = insertelement <4 x float> %1, float %a, i32 1
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; float argument passed in $f12
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; MIPS32-DAG: insve.w [[R1]][1], $w12[0]
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store <4 x float> %2, <4 x float>* @v4f32
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; MIPS32-DAG: st.w [[R1]]
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ret void
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; MIPS32: .size insert_v4f32
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}
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define void @insert_v2f64(double %a) nounwind {
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; MIPS32: insert_v2f64:
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%1 = load <2 x double>* @v2f64
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; MIPS32-DAG: ld.d [[R1:\$w[0-9]+]],
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%2 = insertelement <2 x double> %1, double %a, i32 1
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; double argument passed in $f12
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; MIPS32-DAG: insve.d [[R1]][1], $w12[0]
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store <2 x double> %2, <2 x double>* @v2f64
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; MIPS32-DAG: st.d [[R1]]
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ret void
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; MIPS32: .size insert_v2f64
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}
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