Simon Pilgrim 68688c119a [X86][SSE] Tidied up vector CTLZ/CTTZ. NFCI. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242645 91177308-0d34-0410-b5e6-96231b3b80d8		2015-07-19 17:09:43 +00:00
..
AArch64	[RAGreedy] Add an experimental deferred spilling feature.	2015-07-17 23:04:06 +00:00
AMDGPU	Only do fmul (fadd x, x), c combine if the fadd only has one use	2015-07-17 01:14:35 +00:00
ARM	ARM: Enable MachineScheduler and disable PostRAScheduler for swift.	2015-07-17 23:18:30 +00:00
BPF
CPP
Generic
Hexagon
Inputs
Mips	[SDAG] Optimize unordered comparison in soft-float mode (patch by Anton Nadolskiy)	2015-07-15 08:39:35 +00:00
MIR	MIR Parser: Allow the dollar characters in all of the identifier tokens.	2015-07-17 22:48:04 +00:00
MSP430
NVPTX	Use inbounds GEPs for memcpy and memset lowering	2015-07-17 16:42:33 +00:00
PowerPC	[PowerPC] v4i32 is a VSRCRegClass	2015-07-16 21:14:07 +00:00
SPARC
SystemZ
Thumb
Thumb2	ARM: Add scheduling information for LDRLIT instructions to swift scheduling model	2015-07-17 23:18:26 +00:00
WebAssembly
WinEH
X86	[X86][SSE] Tidied up vector CTLZ/CTTZ. NFCI.	2015-07-19 17:09:43 +00:00
XCore