mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-06-09 23:29:52 +00:00
fa2c240c15
The XformToShuffleWithZero method currently checks AND masks at the per-lane level for all-one and all-zero constants and attempts to convert them to legal shuffle clear masks. This patch generalises XformToShuffleWithZero, splitting and checking the sub-lanes of the constants down to the byte level to see if any legal shuffle clear masks are possible. This allows a lot of masks (often from legalization or truncation) to be folded into existing shuffle patterns and removes a lot of constant mask loading. There are a few examples of poor shuffle lowering that are exposed by this patch that will be cleaned up in future patches (e.g. merging shuffles that are separated by bitcasts, x86 legalized v8i8 zero extension uses PMOVZX+AND+AND instead of AND+PMOVZX, etc.) Differential Revision: http://reviews.llvm.org/D11518 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243831 91177308-0d34-0410-b5e6-96231b3b80d8
152 lines
4.6 KiB
LLVM
152 lines
4.6 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
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define <4 x i32> @trunc4(<4 x i64> %A) nounwind {
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; CHECK-LABEL: trunc4:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vmovdqa {{.*#+}} ymm1 = <0,2,4,6,u,u,u,u>
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; CHECK-NEXT: vpermd %ymm0, %ymm1, %ymm0
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%B = trunc <4 x i64> %A to <4 x i32>
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ret <4 x i32>%B
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}
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define <8 x i16> @trunc8(<8 x i32> %A) nounwind {
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; CHECK-LABEL: trunc8:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13],zero,zero,zero,zero,zero,zero,zero,zero,ymm0[16,17,20,21,24,25,28,29],zero,zero,zero,zero,zero,zero,zero,zero
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; CHECK-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%B = trunc <8 x i32> %A to <8 x i16>
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ret <8 x i16>%B
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}
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define <4 x i64> @sext4(<4 x i32> %A) nounwind {
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; CHECK-LABEL: sext4:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxdq %xmm0, %ymm0
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; CHECK-NEXT: retq
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%B = sext <4 x i32> %A to <4 x i64>
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ret <4 x i64>%B
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}
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define <8 x i32> @sext8(<8 x i16> %A) nounwind {
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; CHECK-LABEL: sext8:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxwd %xmm0, %ymm0
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; CHECK-NEXT: retq
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%B = sext <8 x i16> %A to <8 x i32>
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ret <8 x i32>%B
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}
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define <4 x i64> @zext4(<4 x i32> %A) nounwind {
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; CHECK-LABEL: zext4:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
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; CHECK-NEXT: retq
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%B = zext <4 x i32> %A to <4 x i64>
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ret <4 x i64>%B
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}
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define <8 x i32> @zext8(<8 x i16> %A) nounwind {
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; CHECK-LABEL: zext8:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; CHECK-NEXT: retq
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%B = zext <8 x i16> %A to <8 x i32>
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ret <8 x i32>%B
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}
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define <8 x i32> @zext_8i8_8i32(<8 x i8> %A) nounwind {
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; CHECK-LABEL: zext_8i8_8i32:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; CHECK-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
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; CHECK-NEXT: retq
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%B = zext <8 x i8> %A to <8 x i32>
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ret <8 x i32>%B
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}
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define <16 x i16> @zext_16i8_16i16(<16 x i8> %z) {
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; CHECK-LABEL: zext_16i8_16i16:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
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; CHECK-NEXT: retq
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%t = zext <16 x i8> %z to <16 x i16>
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ret <16 x i16> %t
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}
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define <16 x i16> @sext_16i8_16i16(<16 x i8> %z) {
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; CHECK-LABEL: sext_16i8_16i16:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxbw %xmm0, %ymm0
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; CHECK-NEXT: retq
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%t = sext <16 x i8> %z to <16 x i16>
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ret <16 x i16> %t
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}
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define <16 x i8> @trunc_16i16_16i8(<16 x i16> %z) {
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; CHECK-LABEL: trunc_16i16_16i8:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vextracti128 $1, %ymm0, %xmm1
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; CHECK-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
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; CHECK-NEXT: vpshufb %xmm2, %xmm1, %xmm1
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; CHECK-NEXT: vpshufb %xmm2, %xmm0, %xmm0
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; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%t = trunc <16 x i16> %z to <16 x i8>
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ret <16 x i8> %t
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}
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define <4 x i64> @load_sext_test1(<4 x i32> *%ptr) {
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; CHECK-LABEL: load_sext_test1:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxdq (%rdi), %ymm0
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; CHECK-NEXT: retq
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%X = load <4 x i32>, <4 x i32>* %ptr
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%Y = sext <4 x i32> %X to <4 x i64>
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ret <4 x i64>%Y
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}
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define <4 x i64> @load_sext_test2(<4 x i8> *%ptr) {
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; CHECK-LABEL: load_sext_test2:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxbq (%rdi), %ymm0
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; CHECK-NEXT: retq
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%X = load <4 x i8>, <4 x i8>* %ptr
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%Y = sext <4 x i8> %X to <4 x i64>
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ret <4 x i64>%Y
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}
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define <4 x i64> @load_sext_test3(<4 x i16> *%ptr) {
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; CHECK-LABEL: load_sext_test3:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxwq (%rdi), %ymm0
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; CHECK-NEXT: retq
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%X = load <4 x i16>, <4 x i16>* %ptr
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%Y = sext <4 x i16> %X to <4 x i64>
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ret <4 x i64>%Y
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}
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define <8 x i32> @load_sext_test4(<8 x i16> *%ptr) {
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; CHECK-LABEL: load_sext_test4:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxwd (%rdi), %ymm0
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; CHECK-NEXT: retq
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%X = load <8 x i16>, <8 x i16>* %ptr
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%Y = sext <8 x i16> %X to <8 x i32>
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ret <8 x i32>%Y
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}
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define <8 x i32> @load_sext_test5(<8 x i8> *%ptr) {
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; CHECK-LABEL: load_sext_test5:
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; CHECK: ## BB#0:
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; CHECK-NEXT: vpmovsxbd (%rdi), %ymm0
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; CHECK-NEXT: retq
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%X = load <8 x i8>, <8 x i8>* %ptr
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%Y = sext <8 x i8> %X to <8 x i32>
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ret <8 x i32>%Y
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}
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