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fa342faef9
ComplexPattern at the root be generated multiple times, once for each opcode they are part of. This encourages factoring because the opcode checks get treated just like everything else in the matcher. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97439 91177308-0d34-0410-b5e6-96231b3b80d8
253 lines
8.7 KiB
C++
253 lines
8.7 KiB
C++
//===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SelectionDAGISel class, which is used as the common
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// base class for SelectionDAG-based instruction selectors.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
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#define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
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#include "llvm/BasicBlock.h"
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#include "llvm/Pass.h"
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#include "llvm/Constant.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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namespace llvm {
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class FastISel;
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class SelectionDAGBuilder;
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class SDValue;
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class MachineRegisterInfo;
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class MachineBasicBlock;
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class MachineFunction;
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class MachineInstr;
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class MachineModuleInfo;
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class DwarfWriter;
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class TargetLowering;
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class TargetInstrInfo;
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class FunctionLoweringInfo;
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class ScheduleHazardRecognizer;
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class GCFunctionInfo;
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class ScheduleDAGSDNodes;
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/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
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/// pattern-matching instruction selectors.
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class SelectionDAGISel : public MachineFunctionPass {
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public:
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const TargetMachine &TM;
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TargetLowering &TLI;
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FunctionLoweringInfo *FuncInfo;
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MachineFunction *MF;
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MachineRegisterInfo *RegInfo;
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SelectionDAG *CurDAG;
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SelectionDAGBuilder *SDB;
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MachineBasicBlock *BB;
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AliasAnalysis *AA;
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GCFunctionInfo *GFI;
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CodeGenOpt::Level OptLevel;
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static char ID;
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explicit SelectionDAGISel(TargetMachine &tm,
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CodeGenOpt::Level OL = CodeGenOpt::Default);
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virtual ~SelectionDAGISel();
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TargetLowering &getTargetLowering() { return TLI; }
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual bool runOnMachineFunction(MachineFunction &MF);
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unsigned MakeReg(EVT VT);
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virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
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virtual void InstructionSelect() = 0;
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void SelectRootInit() {
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DAGSize = CurDAG->AssignTopologicalOrder();
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}
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/// SelectInlineAsmMemoryOperand - Select the specified address as a target
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/// addressing mode, according to the specified constraint code. If this does
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/// not match or is not implemented, return true. The resultant operands
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/// (which will appear in the machine instruction) should be added to the
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/// OutOps vector.
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virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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char ConstraintCode,
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std::vector<SDValue> &OutOps) {
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return true;
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}
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/// IsProfitableToFold - Returns true if it's profitable to fold the specific
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/// operand node N of U during instruction selection that starts at Root.
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virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
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/// IsLegalToFold - Returns true if the specific operand node N of
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/// U can be folded during instruction selection that starts at Root.
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virtual bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root) const;
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/// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
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/// to use for this target when scheduling the DAG.
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virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer();
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// Opcodes used by the DAG state machine:
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enum BuiltinOpcodes {
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OPC_Scope,
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OPC_RecordNode,
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OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
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OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
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OPC_RecordMemRef,
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OPC_CaptureFlagInput,
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OPC_MoveChild,
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OPC_MoveParent,
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OPC_CheckSame,
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OPC_CheckPatternPredicate,
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OPC_CheckPredicate,
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OPC_CheckOpcode,
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OPC_SwitchOpcode,
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OPC_CheckType,
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OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
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OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
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OPC_CheckChild6Type, OPC_CheckChild7Type,
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OPC_CheckInteger,
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OPC_CheckCondCode,
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OPC_CheckValueType,
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OPC_CheckComplexPat,
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OPC_CheckAndImm, OPC_CheckOrImm,
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OPC_CheckFoldableChainNode,
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OPC_CheckChainCompatible,
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OPC_EmitInteger,
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OPC_EmitRegister,
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OPC_EmitConvertToTarget,
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OPC_EmitMergeInputChains,
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OPC_EmitCopyToReg,
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OPC_EmitNodeXForm,
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OPC_EmitNode,
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OPC_MorphNodeTo,
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OPC_MarkFlagResults,
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OPC_CompleteMatch
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};
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enum {
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OPFL_None = 0, // Node has no chain or flag input and isn't variadic.
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OPFL_Chain = 1, // Node has a chain input.
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OPFL_FlagInput = 2, // Node has a flag input.
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OPFL_FlagOutput = 4, // Node has a flag output.
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OPFL_MemRefs = 8, // Node gets accumulated MemRefs.
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OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs.
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OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs.
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OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs.
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OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs.
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OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs.
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OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs.
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OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs.
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OPFL_VariadicInfo = OPFL_Variadic6
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};
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/// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
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/// number of fixed arity values that should be skipped when copying from the
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/// root.
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static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
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return ((Flags&OPFL_VariadicInfo) >> 4)-1;
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}
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protected:
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/// DAGSize - Size of DAG being instruction selected.
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///
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unsigned DAGSize;
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/// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
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/// by tblgen. Others should not call it.
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void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops);
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// Calls to these predicates are generated by tblgen.
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bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
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int64_t DesiredMaskS) const;
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bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
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int64_t DesiredMaskS) const;
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/// CheckPatternPredicate - This function is generated by tblgen in the
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/// target. It runs the specified pattern predicate and returns true if it
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/// succeeds or false if it fails. The number is a private implementation
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/// detail to the code tblgen produces.
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virtual bool CheckPatternPredicate(unsigned PredNo) const {
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assert(0 && "Tblgen should generate the implementation of this!");
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return 0;
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}
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/// CheckNodePredicate - This function is generated by tblgen in the target.
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/// It runs node predicate number PredNo and returns true if it succeeds or
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/// false if it fails. The number is a private implementation
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/// detail to the code tblgen produces.
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virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
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assert(0 && "Tblgen should generate the implementation of this!");
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return 0;
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}
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virtual bool CheckComplexPattern(SDNode *Root, SDValue N, unsigned PatternNo,
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SmallVectorImpl<SDValue> &Result) {
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assert(0 && "Tblgen should generate the implementation of this!");
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return false;
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}
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virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
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assert(0 && "Tblgen shoudl generate this!");
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return SDValue();
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}
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// Calls to these functions are generated by tblgen.
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SDNode *Select_INLINEASM(SDNode *N);
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SDNode *Select_UNDEF(SDNode *N);
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SDNode *Select_EH_LABEL(SDNode *N);
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SDNode *SelectCodeCommon(SDNode *NodeToMatch,
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const unsigned char *MatcherTable,
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unsigned TableSize);
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void CannotYetSelect(SDNode *N);
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void CannotYetSelectIntrinsic(SDNode *N);
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private:
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void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
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MachineModuleInfo *MMI,
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DwarfWriter *DW,
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const TargetInstrInfo &TII);
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void FinishBasicBlock();
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void SelectBasicBlock(BasicBlock *LLVMBB,
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BasicBlock::iterator Begin,
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BasicBlock::iterator End,
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bool &HadTailCall);
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void CodeGenAndEmitDAG();
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void LowerArguments(BasicBlock *BB);
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void ShrinkDemandedOps();
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void ComputeLiveOutVRegInfo();
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void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
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bool HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, FastISel *F);
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/// Create the scheduler. If a specific scheduler was specified
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/// via the SchedulerRegistry, use it, otherwise select the
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/// one preferred by the target.
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///
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ScheduleDAGSDNodes *CreateScheduler();
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};
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}
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#endif /* LLVM_CODEGEN_SELECTIONDAG_ISEL_H */
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