mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-20 11:29:24 +00:00
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11659 91177308-0d34-0410-b5e6-96231b3b80d8
801 lines
29 KiB
C++
801 lines
29 KiB
C++
//===-- RegAllocLinearScan.cpp - Linear Scan register allocator -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a linear scan register allocator.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/CFG.h"
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#include "Support/Debug.h"
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#include "Support/DepthFirstIterator.h"
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#include "Support/Statistic.h"
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#include "Support/STLExtras.h"
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#include <algorithm>
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using namespace llvm;
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namespace {
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Statistic<> numStores("ra-linearscan", "Number of stores added");
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Statistic<> numLoads ("ra-linearscan", "Number of loads added");
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class PhysRegTracker {
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private:
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const MRegisterInfo* mri_;
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std::vector<unsigned> regUse_;
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public:
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PhysRegTracker(MachineFunction* mf)
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: mri_(mf ? mf->getTarget().getRegisterInfo() : NULL) {
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if (mri_) {
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regUse_.assign(mri_->getNumRegs(), 0);
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}
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}
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PhysRegTracker(const PhysRegTracker& rhs)
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: mri_(rhs.mri_),
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regUse_(rhs.regUse_) {
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}
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const PhysRegTracker& operator=(const PhysRegTracker& rhs) {
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mri_ = rhs.mri_;
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regUse_ = rhs.regUse_;
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return *this;
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}
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void addPhysRegUse(unsigned physReg) {
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++regUse_[physReg];
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for (const unsigned* as = mri_->getAliasSet(physReg); *as; ++as) {
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physReg = *as;
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++regUse_[physReg];
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}
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}
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void delPhysRegUse(unsigned physReg) {
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assert(regUse_[physReg] != 0);
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--regUse_[physReg];
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for (const unsigned* as = mri_->getAliasSet(physReg); *as; ++as) {
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physReg = *as;
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assert(regUse_[physReg] != 0);
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--regUse_[physReg];
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}
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}
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bool isPhysRegAvail(unsigned physReg) const {
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return regUse_[physReg] == 0;
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}
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};
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class RA : public MachineFunctionPass {
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private:
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MachineFunction* mf_;
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const TargetMachine* tm_;
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const TargetInstrInfo* tii_;
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const MRegisterInfo* mri_;
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LiveIntervals* li_;
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typedef std::list<LiveIntervals::Interval*> IntervalPtrs;
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IntervalPtrs unhandled_, fixed_, active_, inactive_, handled_;
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PhysRegTracker prt_;
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typedef std::map<unsigned, unsigned> Virt2PhysMap;
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Virt2PhysMap v2pMap_;
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typedef std::map<unsigned, int> Virt2StackSlotMap;
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Virt2StackSlotMap v2ssMap_;
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int instrAdded_;
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typedef std::vector<float> SpillWeights;
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SpillWeights spillWeights_;
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public:
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RA()
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: prt_(NULL) {
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}
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virtual const char* getPassName() const {
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return "Linear Scan Register Allocator";
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<LiveVariables>();
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AU.addRequired<LiveIntervals>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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/// runOnMachineFunction - register allocate the whole function
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bool runOnMachineFunction(MachineFunction&);
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void releaseMemory();
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private:
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/// initIntervalSets - initializa the four interval sets:
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/// unhandled, fixed, active and inactive
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void initIntervalSets(LiveIntervals::Intervals& li);
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/// processActiveIntervals - expire old intervals and move
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/// non-overlapping ones to the incative list
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void processActiveIntervals(IntervalPtrs::value_type cur);
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/// processInactiveIntervals - expire old intervals and move
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/// overlapping ones to the active list
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void processInactiveIntervals(IntervalPtrs::value_type cur);
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/// updateSpillWeights - updates the spill weights of the
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/// specifed physical register and its weight
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void updateSpillWeights(unsigned reg, SpillWeights::value_type weight);
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/// assignRegOrStackSlotAtInterval - assign a register if one
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/// is available, or spill.
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void assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur);
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/// addSpillCode - adds spill code for interval. The interval
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/// must be modified by LiveIntervals::updateIntervalForSpill.
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void addSpillCode(IntervalPtrs::value_type li, int slot);
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///
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/// register handling helpers
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///
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/// getFreePhysReg - return a free physical register for this
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/// virtual register interval if we have one, otherwise return
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/// 0
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unsigned getFreePhysReg(IntervalPtrs::value_type cur);
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/// assignVirt2PhysReg - assigns the free physical register to
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/// the virtual register passed as arguments
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Virt2PhysMap::iterator
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assignVirt2PhysReg(unsigned virtReg, unsigned physReg);
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/// clearVirtReg - free the physical register associated with this
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/// virtual register and disassociate virtual->physical and
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/// physical->virtual mappings
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void clearVirtReg(Virt2PhysMap::iterator it);
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/// assignVirt2StackSlot - assigns this virtual register to a
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/// stack slot. returns the stack slot
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int assignVirt2StackSlot(unsigned virtReg);
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/// getStackSlot - returns the offset of the specified
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/// register on the stack
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int getStackSlot(unsigned virtReg);
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void printVirtRegAssignment() const {
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std::cerr << "register assignment:\n";
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for (Virt2PhysMap::const_iterator
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i = v2pMap_.begin(), e = v2pMap_.end(); i != e; ++i) {
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assert(i->second != 0);
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std::cerr << "[reg" << i->first << " -> "
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<< mri_->getName(i->second) << "]\n";
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}
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for (Virt2StackSlotMap::const_iterator
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i = v2ssMap_.begin(), e = v2ssMap_.end(); i != e; ++i) {
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std::cerr << '[' << i->first << " -> ss#" << i->second << "]\n";
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}
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std::cerr << '\n';
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}
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void printIntervals(const char* const str,
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RA::IntervalPtrs::const_iterator i,
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RA::IntervalPtrs::const_iterator e) const {
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if (str) std::cerr << str << " intervals:\n";
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for (; i != e; ++i) {
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std::cerr << "\t" << **i << " -> ";
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unsigned reg = (*i)->reg;
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if (MRegisterInfo::isVirtualRegister(reg)) {
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Virt2PhysMap::const_iterator it = v2pMap_.find(reg);
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reg = (it == v2pMap_.end() ? 0 : it->second);
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}
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std::cerr << mri_->getName(reg) << '\n';
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}
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}
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void verifyAssignment() const {
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for (Virt2PhysMap::const_iterator i = v2pMap_.begin(),
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e = v2pMap_.end(); i != e; ++i)
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for (Virt2PhysMap::const_iterator i2 = next(i); i2 != e; ++i2)
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if (MRegisterInfo::isVirtualRegister(i->second) &&
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(i->second == i2->second ||
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mri_->areAliases(i->second, i2->second))) {
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const LiveIntervals::Interval
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&in = li_->getInterval(i->second),
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&in2 = li_->getInterval(i2->second);
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if (in.overlaps(in2)) {
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std::cerr << in << " overlaps " << in2 << '\n';
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assert(0);
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}
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}
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}
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};
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}
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void RA::releaseMemory()
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{
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v2pMap_.clear();
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v2ssMap_.clear();
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unhandled_.clear();
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active_.clear();
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inactive_.clear();
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fixed_.clear();
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handled_.clear();
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}
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bool RA::runOnMachineFunction(MachineFunction &fn) {
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mf_ = &fn;
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tm_ = &fn.getTarget();
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tii_ = &tm_->getInstrInfo();
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mri_ = tm_->getRegisterInfo();
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li_ = &getAnalysis<LiveIntervals>();
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prt_ = PhysRegTracker(mf_);
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initIntervalSets(li_->getIntervals());
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// linear scan algorithm
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DEBUG(std::cerr << "********** LINEAR SCAN **********\n");
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DEBUG(std::cerr << "********** Function: "
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<< mf_->getFunction()->getName() << '\n');
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DEBUG(printIntervals("unhandled", unhandled_.begin(), unhandled_.end()));
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DEBUG(printIntervals("fixed", fixed_.begin(), fixed_.end()));
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DEBUG(printIntervals("active", active_.begin(), active_.end()));
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DEBUG(printIntervals("inactive", inactive_.begin(), inactive_.end()));
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while (!unhandled_.empty() || !fixed_.empty()) {
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// pick the interval with the earliest start point
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IntervalPtrs::value_type cur;
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if (fixed_.empty()) {
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cur = unhandled_.front();
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unhandled_.pop_front();
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}
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else if (unhandled_.empty()) {
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cur = fixed_.front();
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fixed_.pop_front();
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}
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else if (unhandled_.front()->start() < fixed_.front()->start()) {
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cur = unhandled_.front();
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unhandled_.pop_front();
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}
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else {
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cur = fixed_.front();
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fixed_.pop_front();
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}
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DEBUG(std::cerr << "\n*** CURRENT ***: " << *cur << '\n');
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processActiveIntervals(cur);
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processInactiveIntervals(cur);
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// if this register is fixed we are done
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if (MRegisterInfo::isPhysicalRegister(cur->reg)) {
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prt_.addPhysRegUse(cur->reg);
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active_.push_back(cur);
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handled_.push_back(cur);
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}
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// otherwise we are allocating a virtual register. try to find
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// a free physical register or spill an interval in order to
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// assign it one (we could spill the current though).
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else {
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assignRegOrStackSlotAtInterval(cur);
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}
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DEBUG(printIntervals("active", active_.begin(), active_.end()));
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DEBUG(printIntervals("inactive", inactive_.begin(), inactive_.end()));
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// DEBUG(verifyAssignment());
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}
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// expire any remaining active intervals
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for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
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unsigned reg = (*i)->reg;
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DEBUG(std::cerr << "\tinterval " << **i << " expired\n");
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if (MRegisterInfo::isVirtualRegister(reg)) {
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reg = v2pMap_[reg];
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}
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prt_.delPhysRegUse(reg);
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}
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DEBUG(printVirtRegAssignment());
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DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n");
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DEBUG(std::cerr << "********** Function: "
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<< mf_->getFunction()->getName() << '\n');
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for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
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mbbi != mbbe; ++mbbi) {
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instrAdded_ = 0;
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for (MachineBasicBlock::iterator mii = mbbi->begin(), mie = mbbi->end();
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mii != mie; ++mii) {
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DEBUG(
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std::cerr << '[';
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unsigned index = li_->getInstructionIndex(mii);
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if (index == std::numeric_limits<unsigned>::max())
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std::cerr << '*';
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else
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std::cerr << index;
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std::cerr << "]\t";
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mii->print(std::cerr, *tm_));
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// use our current mapping and actually replace every
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// virtual register with its allocated physical registers
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DEBUG(std::cerr << "\t");
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for (unsigned i = 0, e = mii->getNumOperands();
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i != e; ++i) {
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MachineOperand& op = mii->getOperand(i);
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if (op.isRegister() &&
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MRegisterInfo::isVirtualRegister(op.getReg())) {
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unsigned virtReg = op.getReg();
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Virt2PhysMap::iterator it = v2pMap_.find(virtReg);
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assert(it != v2pMap_.end() &&
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"all virtual registers must be allocated");
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unsigned physReg = it->second;
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assert(MRegisterInfo::isPhysicalRegister(physReg));
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DEBUG(std::cerr << "\t[reg" << virtReg
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<< " -> " << mri_->getName(physReg) << ']');
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mii->SetMachineOperandReg(i, physReg);
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}
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}
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DEBUG(std::cerr << '\n');
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}
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}
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DEBUG(std::cerr << "********** MACHINEINSTRS **********\n");
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DEBUG(
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for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
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mbbi != mbbe; ++mbbi) {
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for (MachineBasicBlock::iterator mii = mbbi->begin(),
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mie = mbbi->end(); mii != mie; ++mii) {
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unsigned index = li_->getInstructionIndex(mii);
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if (index == std::numeric_limits<unsigned>::max())
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std::cerr << "*\t";
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else
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std::cerr << index << '\t';
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mii->print(std::cerr, *tm_);
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}
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});
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return true;
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}
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void RA::initIntervalSets(LiveIntervals::Intervals& li)
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{
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assert(unhandled_.empty() && fixed_.empty() &&
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active_.empty() && inactive_.empty() &&
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"interval sets should be empty on initialization");
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for (LiveIntervals::Intervals::iterator i = li.begin(), e = li.end();
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i != e; ++i) {
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if (MRegisterInfo::isPhysicalRegister(i->reg))
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fixed_.push_back(&*i);
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else
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unhandled_.push_back(&*i);
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}
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}
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void RA::processActiveIntervals(IntervalPtrs::value_type cur)
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{
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DEBUG(std::cerr << "\tprocessing active intervals:\n");
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for (IntervalPtrs::iterator i = active_.begin(); i != active_.end();) {
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unsigned reg = (*i)->reg;
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// remove expired intervals
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if ((*i)->expiredAt(cur->start())) {
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DEBUG(std::cerr << "\t\tinterval " << **i << " expired\n");
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if (MRegisterInfo::isVirtualRegister(reg)) {
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reg = v2pMap_[reg];
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}
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prt_.delPhysRegUse(reg);
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// remove from active
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i = active_.erase(i);
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}
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// move inactive intervals to inactive list
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else if (!(*i)->liveAt(cur->start())) {
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DEBUG(std::cerr << "\t\tinterval " << **i << " inactive\n");
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if (MRegisterInfo::isVirtualRegister(reg)) {
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reg = v2pMap_[reg];
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}
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prt_.delPhysRegUse(reg);
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// add to inactive
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inactive_.push_back(*i);
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// remove from active
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i = active_.erase(i);
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}
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else {
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++i;
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}
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}
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}
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void RA::processInactiveIntervals(IntervalPtrs::value_type cur)
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{
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DEBUG(std::cerr << "\tprocessing inactive intervals:\n");
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for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end();) {
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unsigned reg = (*i)->reg;
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// remove expired intervals
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if ((*i)->expiredAt(cur->start())) {
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DEBUG(std::cerr << "\t\tinterval " << **i << " expired\n");
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// remove from inactive
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i = inactive_.erase(i);
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}
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// move re-activated intervals in active list
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else if ((*i)->liveAt(cur->start())) {
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DEBUG(std::cerr << "\t\tinterval " << **i << " active\n");
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if (MRegisterInfo::isVirtualRegister(reg)) {
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reg = v2pMap_[reg];
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}
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prt_.addPhysRegUse(reg);
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// add to active
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active_.push_back(*i);
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// remove from inactive
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i = inactive_.erase(i);
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}
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else {
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++i;
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}
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}
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}
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void RA::updateSpillWeights(unsigned reg, SpillWeights::value_type weight)
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{
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spillWeights_[reg] += weight;
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for (const unsigned* as = mri_->getAliasSet(reg); *as; ++as)
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spillWeights_[*as] += weight;
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}
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void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur)
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{
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DEBUG(std::cerr << "\tallocating current interval: ");
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PhysRegTracker backupPrt = prt_;
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spillWeights_.assign(mri_->getNumRegs(), 0.0);
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// for each interval in active update spill weights
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for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end();
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i != e; ++i) {
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unsigned reg = (*i)->reg;
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if (MRegisterInfo::isVirtualRegister(reg))
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reg = v2pMap_[reg];
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updateSpillWeights(reg, (*i)->weight);
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}
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// for every interval in inactive we overlap with, mark the
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// register as not free and update spill weights
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for (IntervalPtrs::const_iterator i = inactive_.begin(),
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e = inactive_.end(); i != e; ++i) {
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if (cur->overlaps(**i)) {
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unsigned reg = (*i)->reg;
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if (MRegisterInfo::isVirtualRegister(reg))
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reg = v2pMap_[reg];
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prt_.addPhysRegUse(reg);
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updateSpillWeights(reg, (*i)->weight);
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}
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}
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// for every interval in fixed we overlap with,
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// mark the register as not free and update spill weights
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for (IntervalPtrs::const_iterator i = fixed_.begin(),
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e = fixed_.end(); i != e; ++i) {
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if (cur->overlaps(**i)) {
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unsigned reg = (*i)->reg;
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prt_.addPhysRegUse(reg);
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updateSpillWeights(reg, (*i)->weight);
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}
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}
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unsigned physReg = getFreePhysReg(cur);
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// restore the physical register tracker
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prt_ = backupPrt;
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// if we find a free register, we are done: assign this virtual to
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// the free physical register and add this interval to the active
|
|
// list.
|
|
if (physReg) {
|
|
DEBUG(std::cerr << mri_->getName(physReg) << '\n');
|
|
assignVirt2PhysReg(cur->reg, physReg);
|
|
active_.push_back(cur);
|
|
handled_.push_back(cur);
|
|
return;
|
|
}
|
|
DEBUG(std::cerr << "no free registers\n");
|
|
|
|
DEBUG(std::cerr << "\tassigning stack slot at interval "<< *cur << ":\n");
|
|
|
|
float minWeight = std::numeric_limits<float>::infinity();
|
|
unsigned minReg = 0;
|
|
const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(cur->reg);
|
|
for (TargetRegisterClass::iterator i = rc->allocation_order_begin(*mf_);
|
|
i != rc->allocation_order_end(*mf_); ++i) {
|
|
unsigned reg = *i;
|
|
if (minWeight > spillWeights_[reg]) {
|
|
minWeight = spillWeights_[reg];
|
|
minReg = reg;
|
|
}
|
|
}
|
|
DEBUG(std::cerr << "\t\tregister with min weight: "
|
|
<< mri_->getName(minReg) << " (" << minWeight << ")\n");
|
|
|
|
// if the current has the minimum weight, we need to modify it,
|
|
// push it back in unhandled and let the linear scan algorithm run
|
|
// again
|
|
if (cur->weight <= minWeight) {
|
|
DEBUG(std::cerr << "\t\t\tspilling(c): " << *cur << '\n';);
|
|
int slot = assignVirt2StackSlot(cur->reg);
|
|
li_->updateSpilledInterval(*cur, slot);
|
|
|
|
// if we didn't eliminate the interval find where to add it
|
|
// back to unhandled. We need to scan since unhandled are
|
|
// sorted on earliest start point and we may have changed our
|
|
// start point.
|
|
if (!cur->empty()) {
|
|
addSpillCode(cur, slot);
|
|
IntervalPtrs::iterator it = unhandled_.begin();
|
|
while (it != unhandled_.end() && (*it)->start() < cur->start())
|
|
++it;
|
|
unhandled_.insert(it, cur);
|
|
}
|
|
return;
|
|
}
|
|
|
|
// push the current interval back to unhandled since we are going
|
|
// to re-run at least this iteration. Since we didn't modify it it
|
|
// should go back right in the front of the list
|
|
unhandled_.push_front(cur);
|
|
|
|
// otherwise we spill all intervals aliasing the register with
|
|
// minimum weight, rollback to the interval with the earliest
|
|
// start point and let the linear scan algorithm run again
|
|
std::vector<bool> toSpill(mri_->getNumRegs(), false);
|
|
toSpill[minReg] = true;
|
|
for (const unsigned* as = mri_->getAliasSet(minReg); *as; ++as)
|
|
toSpill[*as] = true;
|
|
unsigned earliestStart = cur->start();
|
|
|
|
for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) {
|
|
unsigned reg = (*i)->reg;
|
|
if (MRegisterInfo::isVirtualRegister(reg) &&
|
|
toSpill[v2pMap_[reg]] &&
|
|
cur->overlaps(**i)) {
|
|
DEBUG(std::cerr << "\t\t\tspilling(a): " << **i << '\n');
|
|
earliestStart = std::min(earliestStart, (*i)->start());
|
|
int slot = assignVirt2StackSlot((*i)->reg);
|
|
li_->updateSpilledInterval(**i, slot);
|
|
addSpillCode(*i, slot);
|
|
}
|
|
}
|
|
for (IntervalPtrs::iterator i = inactive_.begin();
|
|
i != inactive_.end(); ++i) {
|
|
unsigned reg = (*i)->reg;
|
|
if (MRegisterInfo::isVirtualRegister(reg) &&
|
|
toSpill[v2pMap_[reg]] &&
|
|
cur->overlaps(**i)) {
|
|
DEBUG(std::cerr << "\t\t\tspilling(i): " << **i << '\n');
|
|
earliestStart = std::min(earliestStart, (*i)->start());
|
|
int slot = assignVirt2StackSlot((*i)->reg);
|
|
li_->updateSpilledInterval(**i, slot);
|
|
addSpillCode(*i, slot);
|
|
}
|
|
}
|
|
|
|
DEBUG(std::cerr << "\t\trolling back to: " << earliestStart << '\n');
|
|
// scan handled in reverse order and undo each one, restoring the
|
|
// state of unhandled and fixed
|
|
while (!handled_.empty()) {
|
|
IntervalPtrs::value_type i = handled_.back();
|
|
// if this interval starts before t we are done
|
|
if (!i->empty() && i->start() < earliestStart)
|
|
break;
|
|
DEBUG(std::cerr << "\t\t\tundo changes for: " << *i << '\n');
|
|
handled_.pop_back();
|
|
IntervalPtrs::iterator it;
|
|
if ((it = find(active_.begin(), active_.end(), i)) != active_.end()) {
|
|
active_.erase(it);
|
|
if (MRegisterInfo::isPhysicalRegister(i->reg)) {
|
|
fixed_.push_front(i);
|
|
prt_.delPhysRegUse(i->reg);
|
|
}
|
|
else {
|
|
Virt2PhysMap::iterator v2pIt = v2pMap_.find(i->reg);
|
|
clearVirtReg(v2pIt);
|
|
prt_.delPhysRegUse(v2pIt->second);
|
|
if (i->spilled()) {
|
|
if (!i->empty()) {
|
|
IntervalPtrs::iterator it = unhandled_.begin();
|
|
while (it != unhandled_.end() &&
|
|
(*it)->start() < i->start())
|
|
++it;
|
|
unhandled_.insert(it, i);
|
|
}
|
|
}
|
|
else
|
|
unhandled_.push_front(i);
|
|
|
|
}
|
|
}
|
|
else if ((it = find(inactive_.begin(), inactive_.end(), i)) != inactive_.end()) {
|
|
inactive_.erase(it);
|
|
if (MRegisterInfo::isPhysicalRegister(i->reg))
|
|
fixed_.push_front(i);
|
|
else {
|
|
Virt2PhysMap::iterator v2pIt = v2pMap_.find(i->reg);
|
|
clearVirtReg(v2pIt);
|
|
if (i->spilled()) {
|
|
if (!i->empty()) {
|
|
IntervalPtrs::iterator it = unhandled_.begin();
|
|
while (it != unhandled_.end() &&
|
|
(*it)->start() < i->start())
|
|
++it;
|
|
unhandled_.insert(it, i);
|
|
}
|
|
}
|
|
else
|
|
unhandled_.push_front(i);
|
|
}
|
|
}
|
|
else {
|
|
if (MRegisterInfo::isPhysicalRegister(i->reg))
|
|
fixed_.push_front(i);
|
|
else {
|
|
Virt2PhysMap::iterator v2pIt = v2pMap_.find(i->reg);
|
|
clearVirtReg(v2pIt);
|
|
unhandled_.push_front(i);
|
|
}
|
|
}
|
|
}
|
|
|
|
// scan the rest and undo each interval that expired after t and
|
|
// insert it in active (the next iteration of the algorithm will
|
|
// put it in inactive if required)
|
|
IntervalPtrs::iterator i = handled_.begin(), e = handled_.end();
|
|
for (; i != e; ++i) {
|
|
if (!(*i)->expiredAt(earliestStart) && (*i)->expiredAt(cur->start())) {
|
|
DEBUG(std::cerr << "\t\t\tundo changes for: " << **i << '\n');
|
|
active_.push_back(*i);
|
|
if (MRegisterInfo::isPhysicalRegister((*i)->reg))
|
|
prt_.addPhysRegUse((*i)->reg);
|
|
else {
|
|
assert(v2pMap_.count((*i)->reg));
|
|
prt_.addPhysRegUse(v2pMap_.find((*i)->reg)->second);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
void RA::addSpillCode(IntervalPtrs::value_type li, int slot)
|
|
{
|
|
// We scan the instructions corresponding to each range. We load
|
|
// when we have a use and spill at end of basic blocks or end of
|
|
// ranges only if the register was modified.
|
|
const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li->reg);
|
|
|
|
for (LiveIntervals::Interval::Ranges::iterator i = li->ranges.begin(),
|
|
e = li->ranges.end(); i != e; ++i) {
|
|
unsigned index = i->first;
|
|
unsigned end = i->second;
|
|
|
|
bool loaded = false;
|
|
|
|
// skip deleted instructions. getInstructionFromIndex returns
|
|
// null if the instruction was deleted (because of coalescing
|
|
// for example)
|
|
while (!li_->getInstructionFromIndex(index))
|
|
index += LiveIntervals::InstrSlots::NUM;
|
|
MachineBasicBlock::iterator mi = li_->getInstructionFromIndex(index);
|
|
MachineBasicBlock* mbb = mi->getParent();
|
|
assert(mbb && "machine instruction not bound to basic block");
|
|
|
|
for (; index < end; index += LiveIntervals::InstrSlots::NUM) {
|
|
// ignore deleted instructions
|
|
while (!li_->getInstructionFromIndex(index)) index += 2;
|
|
mi = li_->getInstructionFromIndex(index);
|
|
DEBUG(std::cerr << "\t\t\t\texamining: \t\t\t\t\t"
|
|
<< LiveIntervals::getBaseIndex(index) << '\t';
|
|
mi->print(std::cerr, *tm_));
|
|
|
|
// if it is used in this instruction load it
|
|
for (unsigned i = 0; i < mi->getNumOperands(); ++i) {
|
|
MachineOperand& mop = mi->getOperand(i);
|
|
if (mop.isRegister() && mop.getReg() == li->reg &&
|
|
mop.isUse() && !loaded) {
|
|
loaded = true;
|
|
mri_->loadRegFromStackSlot(*mbb, mi, li->reg, slot, rc);
|
|
++numLoads;
|
|
DEBUG(std::cerr << "\t\t\t\tadded load for reg" << li->reg
|
|
<< " from ss#" << slot << " before: \t"
|
|
<< LiveIntervals::getBaseIndex(index) << '\t';
|
|
mi->print(std::cerr, *tm_));
|
|
}
|
|
}
|
|
|
|
// if it is defined in this instruction mark as dirty
|
|
for (unsigned i = 0; i < mi->getNumOperands(); ++i) {
|
|
MachineOperand& mop = mi->getOperand(i);
|
|
if (mop.isRegister() && mop.getReg() == li->reg &&
|
|
mop.isDef()) {
|
|
loaded = true;
|
|
|
|
mri_->storeRegToStackSlot(*mbb, next(mi), li->reg, slot,rc);
|
|
++numStores;
|
|
DEBUG(std::cerr << "\t\t\t\tadded store for reg" << li->reg
|
|
<< " to ss#" << slot << " after: \t\t"
|
|
<< LiveIntervals::getBaseIndex(index) << " \t";
|
|
mi->print(std::cerr, *tm_));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
unsigned RA::getFreePhysReg(IntervalPtrs::value_type cur)
|
|
{
|
|
const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(cur->reg);
|
|
|
|
for (TargetRegisterClass::iterator i = rc->allocation_order_begin(*mf_);
|
|
i != rc->allocation_order_end(*mf_); ++i) {
|
|
unsigned reg = *i;
|
|
if (prt_.isPhysRegAvail(reg))
|
|
return reg;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
RA::Virt2PhysMap::iterator
|
|
RA::assignVirt2PhysReg(unsigned virtReg, unsigned physReg)
|
|
{
|
|
bool inserted;
|
|
Virt2PhysMap::iterator it;
|
|
tie(it, inserted) = v2pMap_.insert(std::make_pair(virtReg, physReg));
|
|
assert(inserted && "attempting to assign a virt->phys mapping to an "
|
|
"already mapped register");
|
|
prt_.addPhysRegUse(physReg);
|
|
return it;
|
|
}
|
|
|
|
void RA::clearVirtReg(Virt2PhysMap::iterator it)
|
|
{
|
|
assert(it != v2pMap_.end() &&
|
|
"attempting to clear a not allocated virtual register");
|
|
unsigned physReg = it->second;
|
|
v2pMap_.erase(it);
|
|
DEBUG(std::cerr << "\t\t\tcleared register " << mri_->getName(physReg)
|
|
<< "\n");
|
|
}
|
|
|
|
|
|
int RA::assignVirt2StackSlot(unsigned virtReg)
|
|
{
|
|
const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(virtReg);
|
|
int frameIndex = mf_->getFrameInfo()->CreateStackObject(rc);
|
|
|
|
bool inserted = v2ssMap_.insert(std::make_pair(virtReg, frameIndex)).second;
|
|
assert(inserted && "attempt to assign stack slot to spilled register!");
|
|
return frameIndex;
|
|
}
|
|
|
|
int RA::getStackSlot(unsigned virtReg)
|
|
{
|
|
assert(v2ssMap_.count(virtReg) &&
|
|
"attempt to get stack slot for a non spilled register");
|
|
return v2ssMap_.find(virtReg)->second;
|
|
}
|
|
|
|
FunctionPass* llvm::createLinearScanRegisterAllocator() {
|
|
return new RA();
|
|
}
|