Sean Callanan 1a8b789a4b Eliminated the classification of control registers into %ecr_ ... and %rcr_, leaving just %cr_ which is what people expect. Updated the disassembler to support this unified register set. Added a testcase to verify that the registers continue to be decoded correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8		2010-05-06 20:59:00 +00:00
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bugpoint
buildit	Select an ARM-hosted cross build with a separate makefile target instead of	2010-05-05 22:22:40 +00:00
count
crosstool
emacs
FileCheck
FileUpdate
fpcmp	Remove unnecessary uses of <iostream>.	2010-04-15 03:47:24 +00:00
git
jedit
lint
lit	lit: Allow test_format to be None.	2010-05-05 17:22:35 +00:00
Misc
not
PerfectShuffle
TableGen	Eliminated the classification of control registers into %ecr_	2010-05-06 20:59:00 +00:00
unittest	silence some -Wmissing-field-initializers warnings.	2010-04-18 03:30:32 +00:00
valgrind	Rearrange the suppressions files to be by-architecture instead of by-problem.	2010-05-05 18:39:16 +00:00
vim
cgiplotNLT.pl
check-each-file
codegen-diff
countloc.sh
DSAclean.py
DSAextract.py
findmisopt
findoptdiff
findsym.pl
GenLibDeps.pl
GetSourceVersion
getsrcs.sh
importNLT.pl
llvm-native-gcc
llvm-native-gxx
llvm.grm	Add a polygen rule that reflects the fact that nsw and nuw can be	2010-05-04 00:13:24 +00:00
llvmdo
llvmgrep
Makefile
makellvm
mkpatch
NewNightlyTest.pl
NightlyTest.gnuplot
NightlyTestTemplate.html
NLT.schema
OldenDataRecover.pl
parseNLT.pl
plotNLT.pl
profile.pl
RegressionFinder.pl
UpdateCMakeLists.pl
userloc.pl
webNLT.pl