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44603b67b1
With the foregoing three patches, VSX instructions can be used for little endian. This patch removes the restriction that prevented this, and re-enables the test cases from the first three patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223792 91177308-0d34-0410-b5e6-96231b3b80d8
47 lines
2.3 KiB
LLVM
47 lines
2.3 KiB
LLVM
; RUN: llc -mcpu=pwr8 -mattr=+vsx -O2 -mtriple=powerpc64-unknown-linux-gnu < %s > %t
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; RUN: grep lxvw4x < %t | count 3
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; RUN: grep lxvd2x < %t | count 3
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; RUN: grep stxvw4x < %t | count 3
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; RUN: grep stxvd2x < %t | count 3
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; RUN: llc -mcpu=pwr8 -mattr=+vsx -O0 -fast-isel=1 -mtriple=powerpc64-unknown-linux-gnu < %s > %t
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; RUN: grep lxvw4x < %t | count 3
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; RUN: grep lxvd2x < %t | count 3
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; RUN: grep stxvw4x < %t | count 3
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; RUN: grep stxvd2x < %t | count 3
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; RUN: llc -mcpu=pwr8 -mattr=+vsx -O2 -mtriple=powerpc64le-unknown-linux-gnu < %s > %t
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; RUN: grep lxvd2x < %t | count 6
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; RUN: grep stxvd2x < %t | count 6
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; RUN: grep xxpermdi < %t | count 12
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@vsi = global <4 x i32> <i32 -1, i32 2, i32 -3, i32 4>, align 16
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@vui = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
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@vf = global <4 x float> <float -1.500000e+00, float 2.500000e+00, float -3.500000e+00, float 4.500000e+00>, align 16
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@vsll = global <2 x i64> <i64 255, i64 -937>, align 16
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@vull = global <2 x i64> <i64 1447, i64 2894>, align 16
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@vd = global <2 x double> <double 3.500000e+00, double -7.500000e+00>, align 16
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@res_vsi = common global <4 x i32> zeroinitializer, align 16
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@res_vui = common global <4 x i32> zeroinitializer, align 16
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@res_vf = common global <4 x float> zeroinitializer, align 16
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@res_vsll = common global <2 x i64> zeroinitializer, align 16
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@res_vull = common global <2 x i64> zeroinitializer, align 16
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@res_vd = common global <2 x double> zeroinitializer, align 16
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; Function Attrs: nounwind
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define void @test1() {
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entry:
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%0 = load <4 x i32>* @vsi, align 16
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%1 = load <4 x i32>* @vui, align 16
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%2 = load <4 x i32>* bitcast (<4 x float>* @vf to <4 x i32>*), align 16
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%3 = load <2 x double>* bitcast (<2 x i64>* @vsll to <2 x double>*), align 16
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%4 = load <2 x double>* bitcast (<2 x i64>* @vull to <2 x double>*), align 16
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%5 = load <2 x double>* @vd, align 16
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store <4 x i32> %0, <4 x i32>* @res_vsi, align 16
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store <4 x i32> %1, <4 x i32>* @res_vui, align 16
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store <4 x i32> %2, <4 x i32>* bitcast (<4 x float>* @res_vf to <4 x i32>*), align 16
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store <2 x double> %3, <2 x double>* bitcast (<2 x i64>* @res_vsll to <2 x double>*), align 16
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store <2 x double> %4, <2 x double>* bitcast (<2 x i64>* @res_vull to <2 x double>*), align 16
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store <2 x double> %5, <2 x double>* @res_vd, align 16
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ret void
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}
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