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acd79ce0ad
When we had a sequence like:
s1 = VLDRS [r0, 1], Q0<imp-def>
s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def>
s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def>
s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def>
we were gathering the {s0, s1} loads below the s3 load. This is fine,
but confused the verifier since now the s3 load had Q0<imp-use> with
no definition above it.
This should mark such uses <undef> as well. The liveness structure at
the beginning and end of the block is unaffected, and the true sN
definitions should prevent any dodgy reorderings being introduced
elsewhere.
rdar://problem/15124449
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192344 91177308-0d34-0410-b5e6-96231b3b80d8
41 lines
1.6 KiB
LLVM
41 lines
1.6 KiB
LLVM
; RUN: llc -mtriple thumbv7-apple-ios -verify-machineinstrs -o - %s | FileCheck %s
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; ARM load store optimizer was dealing with a sequence like:
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; s1 = VLDRS [r0, 1], Q0<imp-def>
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; s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def>
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; s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def>
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; s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def>
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;
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; It decided to combine the {s0, s1} loads into a single instruction in the
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; third position. However, this leaves the instruction defining s3 with a stray
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; imp-use of Q0, which is undefined.
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;
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; The verifier catches this, so this test just makes sure that appropriate
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; liveness flags are added.
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;
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; I believe the change will be tested as long as the vldmia is not the first of
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; the loads. Earlier optimisations may perturb the output over time, but
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; fiddling the indices should be sufficient to restore the test.
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define arm_aapcs_vfpcc <4 x float> @foo(float* %ptr) {
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; CHECK-LABEL: foo:
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; CHECK: vldr s3, [r0, #8]
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; CHECK: vldmia r0, {s0, s1}
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; CHECK: vldr s2, [r0, #16]
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%off0 = getelementptr float* %ptr, i32 0
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%val0 = load float* %off0
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%off1 = getelementptr float* %ptr, i32 1
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%val1 = load float* %off1
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%off4 = getelementptr float* %ptr, i32 4
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%val4 = load float* %off4
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%off2 = getelementptr float* %ptr, i32 2
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%val2 = load float* %off2
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%vec1 = insertelement <4 x float> undef, float %val0, i32 0
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%vec2 = insertelement <4 x float> %vec1, float %val1, i32 1
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%vec3 = insertelement <4 x float> %vec2, float %val4, i32 2
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%vec4 = insertelement <4 x float> %vec3, float %val2, i32 3
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ret <4 x float> %vec4
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}
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