mirror of
https://github.com/c64scene-ar/llvm-6502.git
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floating point stack instructions instead of looking for b/w/l/q. This fixes issues where we'd accidentally match fistp to fistpl, when it is in fact an ambiguous instruction. This changes the behavior of llvm-mc to reject fstp, which was the correct fix for rdar://8456389: t.s:1:1: error: ambiguous instructions require an explicit suffix (could be 'fstps', 'fstpl', or 'fstpt') fstp (%rax) it also causes us to correctly reject fistp and fist, which addresses PR8528: t.s:2:1: error: ambiguous instructions require an explicit suffix (could be 'fistps', or 'fistpl') fistp (%rax) ^ t.s:3:1: error: ambiguous instructions require an explicit suffix (could be 'fists', or 'fistl') fist (%rax) ^ Thanks to Ismail Donmez for tracking down the issue here! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118346 91177308-0d34-0410-b5e6-96231b3b80d8
1153 lines
38 KiB
C++
1153 lines
38 KiB
C++
//===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetAsmParser.h"
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#include "X86.h"
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#include "X86Subtarget.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/Target/TargetAsmParser.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCParser/MCAsmLexer.h"
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#include "llvm/MC/MCParser/MCAsmParser.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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struct X86Operand;
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class X86ATTAsmParser : public TargetAsmParser {
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MCAsmParser &Parser;
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TargetMachine &TM;
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protected:
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unsigned Is64Bit : 1;
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private:
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MCAsmParser &getParser() const { return Parser; }
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MCAsmLexer &getLexer() const { return Parser.getLexer(); }
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bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
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bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
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X86Operand *ParseOperand();
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X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
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bool ParseDirectiveWord(unsigned Size, SMLoc L);
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bool MatchAndEmitInstruction(SMLoc IDLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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MCStreamer &Out);
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/// @name Auto-generated Matcher Functions
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/// {
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#define GET_ASSEMBLER_HEADER
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#include "X86GenAsmMatcher.inc"
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/// }
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public:
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X86ATTAsmParser(const Target &T, MCAsmParser &parser, TargetMachine &TM)
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: TargetAsmParser(T), Parser(parser), TM(TM) {
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// Initialize the set of available features.
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setAvailableFeatures(ComputeAvailableFeatures(
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&TM.getSubtarget<X86Subtarget>()));
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}
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virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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virtual bool ParseDirective(AsmToken DirectiveID);
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};
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class X86_32ATTAsmParser : public X86ATTAsmParser {
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public:
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X86_32ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine &TM)
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: X86ATTAsmParser(T, Parser, TM) {
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Is64Bit = false;
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}
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};
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class X86_64ATTAsmParser : public X86ATTAsmParser {
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public:
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X86_64ATTAsmParser(const Target &T, MCAsmParser &Parser, TargetMachine &TM)
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: X86ATTAsmParser(T, Parser, TM) {
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Is64Bit = true;
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}
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};
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} // end anonymous namespace
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/// @name Auto-generated Match Functions
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/// {
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static unsigned MatchRegisterName(StringRef Name);
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/// }
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namespace {
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/// X86Operand - Instances of this class represent a parsed X86 machine
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/// instruction.
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struct X86Operand : public MCParsedAsmOperand {
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enum KindTy {
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Token,
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Register,
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Immediate,
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Memory
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} Kind;
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SMLoc StartLoc, EndLoc;
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union {
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struct {
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const char *Data;
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unsigned Length;
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} Tok;
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struct {
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unsigned RegNo;
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} Reg;
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struct {
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const MCExpr *Val;
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} Imm;
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struct {
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unsigned SegReg;
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const MCExpr *Disp;
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unsigned BaseReg;
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unsigned IndexReg;
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unsigned Scale;
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} Mem;
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};
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X86Operand(KindTy K, SMLoc Start, SMLoc End)
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: Kind(K), StartLoc(Start), EndLoc(End) {}
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/// getStartLoc - Get the location of the first token of this operand.
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SMLoc getStartLoc() const { return StartLoc; }
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/// getEndLoc - Get the location of the last token of this operand.
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SMLoc getEndLoc() const { return EndLoc; }
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virtual void dump(raw_ostream &OS) const {}
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StringRef getToken() const {
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assert(Kind == Token && "Invalid access!");
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return StringRef(Tok.Data, Tok.Length);
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}
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void setTokenValue(StringRef Value) {
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assert(Kind == Token && "Invalid access!");
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Tok.Data = Value.data();
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Tok.Length = Value.size();
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}
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unsigned getReg() const {
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assert(Kind == Register && "Invalid access!");
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return Reg.RegNo;
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}
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const MCExpr *getImm() const {
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assert(Kind == Immediate && "Invalid access!");
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return Imm.Val;
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}
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const MCExpr *getMemDisp() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.Disp;
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}
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unsigned getMemSegReg() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.SegReg;
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}
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unsigned getMemBaseReg() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.BaseReg;
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}
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unsigned getMemIndexReg() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.IndexReg;
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}
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unsigned getMemScale() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.Scale;
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}
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bool isToken() const {return Kind == Token; }
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bool isImm() const { return Kind == Immediate; }
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bool isImmSExti16i8() const {
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if (!isImm())
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return false;
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// If this isn't a constant expr, just assume it fits and let relaxation
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// handle it.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE)
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return true;
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// Otherwise, check the value is in a range that makes sense for this
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// extension.
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uint64_t Value = CE->getValue();
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return (( Value <= 0x000000000000007FULL)||
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(0x000000000000FF80ULL <= Value && Value <= 0x000000000000FFFFULL)||
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(0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
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}
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bool isImmSExti32i8() const {
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if (!isImm())
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return false;
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// If this isn't a constant expr, just assume it fits and let relaxation
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// handle it.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE)
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return true;
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// Otherwise, check the value is in a range that makes sense for this
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// extension.
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uint64_t Value = CE->getValue();
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return (( Value <= 0x000000000000007FULL)||
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(0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||
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(0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
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}
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bool isImmSExti64i8() const {
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if (!isImm())
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return false;
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// If this isn't a constant expr, just assume it fits and let relaxation
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// handle it.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE)
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return true;
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// Otherwise, check the value is in a range that makes sense for this
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// extension.
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uint64_t Value = CE->getValue();
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return (( Value <= 0x000000000000007FULL)||
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(0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
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}
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bool isImmSExti64i32() const {
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if (!isImm())
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return false;
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// If this isn't a constant expr, just assume it fits and let relaxation
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// handle it.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE)
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return true;
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// Otherwise, check the value is in a range that makes sense for this
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// extension.
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uint64_t Value = CE->getValue();
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return (( Value <= 0x000000007FFFFFFFULL)||
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(0xFFFFFFFF80000000ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));
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}
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bool isMem() const { return Kind == Memory; }
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bool isAbsMem() const {
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return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
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!getMemIndexReg() && getMemScale() == 1;
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}
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bool isReg() const { return Kind == Register; }
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void addExpr(MCInst &Inst, const MCExpr *Expr) const {
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// Add as immediates when possible.
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if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
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Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
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else
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Inst.addOperand(MCOperand::CreateExpr(Expr));
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}
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void addRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getReg()));
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}
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void addImmOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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addExpr(Inst, getImm());
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}
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void addMemOperands(MCInst &Inst, unsigned N) const {
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assert((N == 5) && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
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Inst.addOperand(MCOperand::CreateImm(getMemScale()));
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Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
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addExpr(Inst, getMemDisp());
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Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
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}
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void addAbsMemOperands(MCInst &Inst, unsigned N) const {
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assert((N == 1) && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
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}
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static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
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X86Operand *Res = new X86Operand(Token, Loc, Loc);
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Res->Tok.Data = Str.data();
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Res->Tok.Length = Str.size();
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return Res;
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}
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static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) {
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X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
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Res->Reg.RegNo = RegNo;
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return Res;
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}
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static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
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X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
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Res->Imm.Val = Val;
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return Res;
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}
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/// Create an absolute memory operand.
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static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc,
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SMLoc EndLoc) {
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X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
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Res->Mem.SegReg = 0;
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Res->Mem.Disp = Disp;
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Res->Mem.BaseReg = 0;
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Res->Mem.IndexReg = 0;
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Res->Mem.Scale = 1;
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return Res;
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}
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/// Create a generalized memory operand.
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static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
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unsigned BaseReg, unsigned IndexReg,
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unsigned Scale, SMLoc StartLoc, SMLoc EndLoc) {
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// We should never just have a displacement, that should be parsed as an
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// absolute memory operand.
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assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
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// The scale should always be one of {1,2,4,8}.
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assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
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"Invalid scale!");
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X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
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Res->Mem.SegReg = SegReg;
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Res->Mem.Disp = Disp;
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Res->Mem.BaseReg = BaseReg;
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Res->Mem.IndexReg = IndexReg;
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Res->Mem.Scale = Scale;
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return Res;
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}
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};
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} // end anonymous namespace.
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bool X86ATTAsmParser::ParseRegister(unsigned &RegNo,
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SMLoc &StartLoc, SMLoc &EndLoc) {
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RegNo = 0;
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const AsmToken &TokPercent = Parser.getTok();
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assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!");
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StartLoc = TokPercent.getLoc();
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Parser.Lex(); // Eat percent token.
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const AsmToken &Tok = Parser.getTok();
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if (Tok.isNot(AsmToken::Identifier))
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return Error(Tok.getLoc(), "invalid register name");
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// FIXME: Validate register for the current architecture; we have to do
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// validation later, so maybe there is no need for this here.
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RegNo = MatchRegisterName(Tok.getString());
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// If the match failed, try the register name as lowercase.
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if (RegNo == 0)
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RegNo = MatchRegisterName(LowercaseString(Tok.getString()));
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// FIXME: This should be done using Requires<In32BitMode> and
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// Requires<In64BitMode> so "eiz" usage in 64-bit instructions
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// can be also checked.
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if (RegNo == X86::RIZ && !Is64Bit)
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return Error(Tok.getLoc(), "riz register in 64-bit mode only");
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// Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
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if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
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RegNo = X86::ST0;
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EndLoc = Tok.getLoc();
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Parser.Lex(); // Eat 'st'
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// Check to see if we have '(4)' after %st.
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if (getLexer().isNot(AsmToken::LParen))
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return false;
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// Lex the paren.
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getParser().Lex();
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const AsmToken &IntTok = Parser.getTok();
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if (IntTok.isNot(AsmToken::Integer))
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return Error(IntTok.getLoc(), "expected stack index");
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switch (IntTok.getIntVal()) {
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case 0: RegNo = X86::ST0; break;
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case 1: RegNo = X86::ST1; break;
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case 2: RegNo = X86::ST2; break;
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case 3: RegNo = X86::ST3; break;
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case 4: RegNo = X86::ST4; break;
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case 5: RegNo = X86::ST5; break;
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case 6: RegNo = X86::ST6; break;
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case 7: RegNo = X86::ST7; break;
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default: return Error(IntTok.getLoc(), "invalid stack index");
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}
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if (getParser().Lex().isNot(AsmToken::RParen))
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return Error(Parser.getTok().getLoc(), "expected ')'");
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EndLoc = Tok.getLoc();
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Parser.Lex(); // Eat ')'
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return false;
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}
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// If this is "db[0-7]", match it as an alias
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// for dr[0-7].
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if (RegNo == 0 && Tok.getString().size() == 3 &&
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Tok.getString().startswith("db")) {
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switch (Tok.getString()[2]) {
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case '0': RegNo = X86::DR0; break;
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case '1': RegNo = X86::DR1; break;
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case '2': RegNo = X86::DR2; break;
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case '3': RegNo = X86::DR3; break;
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case '4': RegNo = X86::DR4; break;
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case '5': RegNo = X86::DR5; break;
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case '6': RegNo = X86::DR6; break;
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case '7': RegNo = X86::DR7; break;
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}
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if (RegNo != 0) {
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EndLoc = Tok.getLoc();
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Parser.Lex(); // Eat it.
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return false;
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}
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}
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if (RegNo == 0)
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return Error(Tok.getLoc(), "invalid register name");
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EndLoc = Tok.getLoc();
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Parser.Lex(); // Eat identifier token.
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return false;
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}
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X86Operand *X86ATTAsmParser::ParseOperand() {
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switch (getLexer().getKind()) {
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default:
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// Parse a memory operand with no segment register.
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return ParseMemOperand(0, Parser.getTok().getLoc());
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case AsmToken::Percent: {
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// Read the register.
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unsigned RegNo;
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SMLoc Start, End;
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if (ParseRegister(RegNo, Start, End)) return 0;
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if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
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Error(Start, "eiz and riz can only be used as index registers");
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return 0;
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}
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// If this is a segment register followed by a ':', then this is the start
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// of a memory reference, otherwise this is a normal register reference.
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if (getLexer().isNot(AsmToken::Colon))
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return X86Operand::CreateReg(RegNo, Start, End);
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getParser().Lex(); // Eat the colon.
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return ParseMemOperand(RegNo, Start);
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}
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case AsmToken::Dollar: {
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// $42 -> immediate.
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SMLoc Start = Parser.getTok().getLoc(), End;
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Parser.Lex();
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const MCExpr *Val;
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if (getParser().ParseExpression(Val, End))
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return 0;
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return X86Operand::CreateImm(Val, Start, End);
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}
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}
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}
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/// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
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/// has already been parsed if present.
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X86Operand *X86ATTAsmParser::ParseMemOperand(unsigned SegReg, SMLoc MemStart) {
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// We have to disambiguate a parenthesized expression "(4+5)" from the start
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// of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
|
|
// only way to do this without lookahead is to eat the '(' and see what is
|
|
// after it.
|
|
const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
|
|
if (getLexer().isNot(AsmToken::LParen)) {
|
|
SMLoc ExprEnd;
|
|
if (getParser().ParseExpression(Disp, ExprEnd)) return 0;
|
|
|
|
// After parsing the base expression we could either have a parenthesized
|
|
// memory address or not. If not, return now. If so, eat the (.
|
|
if (getLexer().isNot(AsmToken::LParen)) {
|
|
// Unless we have a segment register, treat this as an immediate.
|
|
if (SegReg == 0)
|
|
return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
|
|
return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
|
|
}
|
|
|
|
// Eat the '('.
|
|
Parser.Lex();
|
|
} else {
|
|
// Okay, we have a '('. We don't know if this is an expression or not, but
|
|
// so we have to eat the ( to see beyond it.
|
|
SMLoc LParenLoc = Parser.getTok().getLoc();
|
|
Parser.Lex(); // Eat the '('.
|
|
|
|
if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
|
|
// Nothing to do here, fall into the code below with the '(' part of the
|
|
// memory operand consumed.
|
|
} else {
|
|
SMLoc ExprEnd;
|
|
|
|
// It must be an parenthesized expression, parse it now.
|
|
if (getParser().ParseParenExpression(Disp, ExprEnd))
|
|
return 0;
|
|
|
|
// After parsing the base expression we could either have a parenthesized
|
|
// memory address or not. If not, return now. If so, eat the (.
|
|
if (getLexer().isNot(AsmToken::LParen)) {
|
|
// Unless we have a segment register, treat this as an immediate.
|
|
if (SegReg == 0)
|
|
return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
|
|
return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
|
|
}
|
|
|
|
// Eat the '('.
|
|
Parser.Lex();
|
|
}
|
|
}
|
|
|
|
// If we reached here, then we just ate the ( of the memory operand. Process
|
|
// the rest of the memory operand.
|
|
unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
|
|
|
|
if (getLexer().is(AsmToken::Percent)) {
|
|
SMLoc L;
|
|
if (ParseRegister(BaseReg, L, L)) return 0;
|
|
if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
|
|
Error(L, "eiz and riz can only be used as index registers");
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
if (getLexer().is(AsmToken::Comma)) {
|
|
Parser.Lex(); // Eat the comma.
|
|
|
|
// Following the comma we should have either an index register, or a scale
|
|
// value. We don't support the later form, but we want to parse it
|
|
// correctly.
|
|
//
|
|
// Not that even though it would be completely consistent to support syntax
|
|
// like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
|
|
if (getLexer().is(AsmToken::Percent)) {
|
|
SMLoc L;
|
|
if (ParseRegister(IndexReg, L, L)) return 0;
|
|
|
|
if (getLexer().isNot(AsmToken::RParen)) {
|
|
// Parse the scale amount:
|
|
// ::= ',' [scale-expression]
|
|
if (getLexer().isNot(AsmToken::Comma)) {
|
|
Error(Parser.getTok().getLoc(),
|
|
"expected comma in scale expression");
|
|
return 0;
|
|
}
|
|
Parser.Lex(); // Eat the comma.
|
|
|
|
if (getLexer().isNot(AsmToken::RParen)) {
|
|
SMLoc Loc = Parser.getTok().getLoc();
|
|
|
|
int64_t ScaleVal;
|
|
if (getParser().ParseAbsoluteExpression(ScaleVal))
|
|
return 0;
|
|
|
|
// Validate the scale amount.
|
|
if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
|
|
Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
|
|
return 0;
|
|
}
|
|
Scale = (unsigned)ScaleVal;
|
|
}
|
|
}
|
|
} else if (getLexer().isNot(AsmToken::RParen)) {
|
|
// A scale amount without an index is ignored.
|
|
// index.
|
|
SMLoc Loc = Parser.getTok().getLoc();
|
|
|
|
int64_t Value;
|
|
if (getParser().ParseAbsoluteExpression(Value))
|
|
return 0;
|
|
|
|
if (Value != 1)
|
|
Warning(Loc, "scale factor without index register is ignored");
|
|
Scale = 1;
|
|
}
|
|
}
|
|
|
|
// Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
|
|
if (getLexer().isNot(AsmToken::RParen)) {
|
|
Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
|
|
return 0;
|
|
}
|
|
SMLoc MemEnd = Parser.getTok().getLoc();
|
|
Parser.Lex(); // Eat the ')'.
|
|
|
|
return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
|
|
MemStart, MemEnd);
|
|
}
|
|
|
|
bool X86ATTAsmParser::
|
|
ParseInstruction(StringRef Name, SMLoc NameLoc,
|
|
SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
|
StringRef PatchedName = Name;
|
|
|
|
// FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
|
|
const MCExpr *ExtraImmOp = 0;
|
|
if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
|
|
(PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
|
|
PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
|
|
bool IsVCMP = PatchedName.startswith("vcmp");
|
|
unsigned SSECCIdx = IsVCMP ? 4 : 3;
|
|
unsigned SSEComparisonCode = StringSwitch<unsigned>(
|
|
PatchedName.slice(SSECCIdx, PatchedName.size() - 2))
|
|
.Case("eq", 0)
|
|
.Case("lt", 1)
|
|
.Case("le", 2)
|
|
.Case("unord", 3)
|
|
.Case("neq", 4)
|
|
.Case("nlt", 5)
|
|
.Case("nle", 6)
|
|
.Case("ord", 7)
|
|
.Case("eq_uq", 8)
|
|
.Case("nge", 9)
|
|
.Case("ngt", 0x0A)
|
|
.Case("false", 0x0B)
|
|
.Case("neq_oq", 0x0C)
|
|
.Case("ge", 0x0D)
|
|
.Case("gt", 0x0E)
|
|
.Case("true", 0x0F)
|
|
.Case("eq_os", 0x10)
|
|
.Case("lt_oq", 0x11)
|
|
.Case("le_oq", 0x12)
|
|
.Case("unord_s", 0x13)
|
|
.Case("neq_us", 0x14)
|
|
.Case("nlt_uq", 0x15)
|
|
.Case("nle_uq", 0x16)
|
|
.Case("ord_s", 0x17)
|
|
.Case("eq_us", 0x18)
|
|
.Case("nge_uq", 0x19)
|
|
.Case("ngt_uq", 0x1A)
|
|
.Case("false_os", 0x1B)
|
|
.Case("neq_os", 0x1C)
|
|
.Case("ge_oq", 0x1D)
|
|
.Case("gt_oq", 0x1E)
|
|
.Case("true_us", 0x1F)
|
|
.Default(~0U);
|
|
if (SSEComparisonCode != ~0U) {
|
|
ExtraImmOp = MCConstantExpr::Create(SSEComparisonCode,
|
|
getParser().getContext());
|
|
if (PatchedName.endswith("ss")) {
|
|
PatchedName = IsVCMP ? "vcmpss" : "cmpss";
|
|
} else if (PatchedName.endswith("sd")) {
|
|
PatchedName = IsVCMP ? "vcmpsd" : "cmpsd";
|
|
} else if (PatchedName.endswith("ps")) {
|
|
PatchedName = IsVCMP ? "vcmpps" : "cmpps";
|
|
} else {
|
|
assert(PatchedName.endswith("pd") && "Unexpected mnemonic!");
|
|
PatchedName = IsVCMP ? "vcmppd" : "cmppd";
|
|
}
|
|
}
|
|
}
|
|
|
|
// FIXME: Hack to recognize vpclmul<src1_quadword, src2_quadword>dq
|
|
if (PatchedName.startswith("vpclmul")) {
|
|
unsigned CLMULQuadWordSelect = StringSwitch<unsigned>(
|
|
PatchedName.slice(7, PatchedName.size() - 2))
|
|
.Case("lqlq", 0x00) // src1[63:0], src2[63:0]
|
|
.Case("hqlq", 0x01) // src1[127:64], src2[63:0]
|
|
.Case("lqhq", 0x10) // src1[63:0], src2[127:64]
|
|
.Case("hqhq", 0x11) // src1[127:64], src2[127:64]
|
|
.Default(~0U);
|
|
if (CLMULQuadWordSelect != ~0U) {
|
|
ExtraImmOp = MCConstantExpr::Create(CLMULQuadWordSelect,
|
|
getParser().getContext());
|
|
assert(PatchedName.endswith("dq") && "Unexpected mnemonic!");
|
|
PatchedName = "vpclmulqdq";
|
|
}
|
|
}
|
|
|
|
Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
|
|
|
|
if (ExtraImmOp)
|
|
Operands.push_back(X86Operand::CreateImm(ExtraImmOp, NameLoc, NameLoc));
|
|
|
|
|
|
// Determine whether this is an instruction prefix.
|
|
bool isPrefix =
|
|
Name == "lock" || Name == "rep" ||
|
|
Name == "repe" || Name == "repz" ||
|
|
Name == "repne" || Name == "repnz";
|
|
|
|
|
|
// This does the actual operand parsing. Don't parse any more if we have a
|
|
// prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
|
|
// just want to parse the "lock" as the first instruction and the "incl" as
|
|
// the next one.
|
|
if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
|
|
|
|
// Parse '*' modifier.
|
|
if (getLexer().is(AsmToken::Star)) {
|
|
SMLoc Loc = Parser.getTok().getLoc();
|
|
Operands.push_back(X86Operand::CreateToken("*", Loc));
|
|
Parser.Lex(); // Eat the star.
|
|
}
|
|
|
|
// Read the first operand.
|
|
if (X86Operand *Op = ParseOperand())
|
|
Operands.push_back(Op);
|
|
else {
|
|
Parser.EatToEndOfStatement();
|
|
return true;
|
|
}
|
|
|
|
while (getLexer().is(AsmToken::Comma)) {
|
|
Parser.Lex(); // Eat the comma.
|
|
|
|
// Parse and remember the operand.
|
|
if (X86Operand *Op = ParseOperand())
|
|
Operands.push_back(Op);
|
|
else {
|
|
Parser.EatToEndOfStatement();
|
|
return true;
|
|
}
|
|
}
|
|
|
|
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
Parser.EatToEndOfStatement();
|
|
return TokError("unexpected token in argument list");
|
|
}
|
|
}
|
|
|
|
if (getLexer().is(AsmToken::EndOfStatement))
|
|
Parser.Lex(); // Consume the EndOfStatement
|
|
|
|
// Hack to allow 'movq <largeimm>, <reg>' as an alias for movabsq.
|
|
if ((Name == "movq" || Name == "mov") && Operands.size() == 3 &&
|
|
static_cast<X86Operand*>(Operands[2])->isReg() &&
|
|
static_cast<X86Operand*>(Operands[1])->isImm() &&
|
|
!static_cast<X86Operand*>(Operands[1])->isImmSExti64i32()) {
|
|
delete Operands[0];
|
|
Operands[0] = X86Operand::CreateToken("movabsq", NameLoc);
|
|
}
|
|
|
|
// FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
|
|
// "shift <op>".
|
|
if ((Name.startswith("shr") || Name.startswith("sar") ||
|
|
Name.startswith("shl") || Name.startswith("sal")) &&
|
|
Operands.size() == 3) {
|
|
X86Operand *Op1 = static_cast<X86Operand*>(Operands[1]);
|
|
if (Op1->isImm() && isa<MCConstantExpr>(Op1->getImm()) &&
|
|
cast<MCConstantExpr>(Op1->getImm())->getValue() == 1) {
|
|
delete Operands[1];
|
|
Operands.erase(Operands.begin() + 1);
|
|
}
|
|
}
|
|
|
|
// FIXME: Hack to handle recognize "rc[lr] <op>" -> "rcl $1, <op>".
|
|
if ((Name.startswith("rcl") || Name.startswith("rcr")) &&
|
|
Operands.size() == 2) {
|
|
const MCExpr *One = MCConstantExpr::Create(1, getParser().getContext());
|
|
Operands.push_back(X86Operand::CreateImm(One, NameLoc, NameLoc));
|
|
std::swap(Operands[1], Operands[2]);
|
|
}
|
|
|
|
// FIXME: Hack to handle recognize "sh[lr]d op,op" -> "shld $1, op,op".
|
|
if ((Name.startswith("shld") || Name.startswith("shrd")) &&
|
|
Operands.size() == 3) {
|
|
const MCExpr *One = MCConstantExpr::Create(1, getParser().getContext());
|
|
Operands.insert(Operands.begin()+1,
|
|
X86Operand::CreateImm(One, NameLoc, NameLoc));
|
|
}
|
|
|
|
|
|
// FIXME: Hack to handle recognize "in[bwl] <op>". Canonicalize it to
|
|
// "inb <op>, %al".
|
|
if ((Name == "inb" || Name == "inw" || Name == "inl") &&
|
|
Operands.size() == 2) {
|
|
unsigned Reg;
|
|
if (Name[2] == 'b')
|
|
Reg = MatchRegisterName("al");
|
|
else if (Name[2] == 'w')
|
|
Reg = MatchRegisterName("ax");
|
|
else
|
|
Reg = MatchRegisterName("eax");
|
|
SMLoc Loc = Operands.back()->getEndLoc();
|
|
Operands.push_back(X86Operand::CreateReg(Reg, Loc, Loc));
|
|
}
|
|
|
|
// FIXME: Hack to handle recognize "out[bwl] <op>". Canonicalize it to
|
|
// "outb %al, <op>".
|
|
if ((Name == "outb" || Name == "outw" || Name == "outl") &&
|
|
Operands.size() == 2) {
|
|
unsigned Reg;
|
|
if (Name[3] == 'b')
|
|
Reg = MatchRegisterName("al");
|
|
else if (Name[3] == 'w')
|
|
Reg = MatchRegisterName("ax");
|
|
else
|
|
Reg = MatchRegisterName("eax");
|
|
SMLoc Loc = Operands.back()->getEndLoc();
|
|
Operands.push_back(X86Operand::CreateReg(Reg, Loc, Loc));
|
|
std::swap(Operands[1], Operands[2]);
|
|
}
|
|
|
|
// FIXME: Hack to handle "out[bwl]? %al, (%dx)" -> "outb %al, %dx".
|
|
if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") &&
|
|
Operands.size() == 3) {
|
|
X86Operand &Op = *(X86Operand*)Operands.back();
|
|
if (Op.isMem() && Op.Mem.SegReg == 0 &&
|
|
isa<MCConstantExpr>(Op.Mem.Disp) &&
|
|
cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
|
|
Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
|
|
SMLoc Loc = Op.getEndLoc();
|
|
Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
|
|
delete &Op;
|
|
}
|
|
}
|
|
|
|
// FIXME: Hack to handle "f{mul*,add*,sub*,div*} $op, st(0)" the same as
|
|
// "f{mul*,add*,sub*,div*} $op"
|
|
if ((Name.startswith("fmul") || Name.startswith("fadd") ||
|
|
Name.startswith("fsub") || Name.startswith("fdiv")) &&
|
|
Operands.size() == 3 &&
|
|
static_cast<X86Operand*>(Operands[2])->isReg() &&
|
|
static_cast<X86Operand*>(Operands[2])->getReg() == X86::ST0) {
|
|
delete Operands[2];
|
|
Operands.erase(Operands.begin() + 2);
|
|
}
|
|
|
|
// FIXME: Hack to handle "f{mulp,addp} st(0), $op" the same as
|
|
// "f{mulp,addp} $op", since they commute. We also allow fdivrp/fsubrp even
|
|
// though they don't commute, solely because gas does support this.
|
|
if ((Name=="fmulp" || Name=="faddp" || Name=="fsubrp" || Name=="fdivrp") &&
|
|
Operands.size() == 3 &&
|
|
static_cast<X86Operand*>(Operands[1])->isReg() &&
|
|
static_cast<X86Operand*>(Operands[1])->getReg() == X86::ST0) {
|
|
delete Operands[1];
|
|
Operands.erase(Operands.begin() + 1);
|
|
}
|
|
|
|
// FIXME: Hack to handle "imul <imm>, B" which is an alias for "imul <imm>, B,
|
|
// B".
|
|
if (Name.startswith("imul") && Operands.size() == 3 &&
|
|
static_cast<X86Operand*>(Operands[1])->isImm() &&
|
|
static_cast<X86Operand*>(Operands.back())->isReg()) {
|
|
X86Operand *Op = static_cast<X86Operand*>(Operands.back());
|
|
Operands.push_back(X86Operand::CreateReg(Op->getReg(), Op->getStartLoc(),
|
|
Op->getEndLoc()));
|
|
}
|
|
|
|
// 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
|
|
// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
|
|
// errors, since its encoding is the most compact.
|
|
if (Name == "sldt" && Operands.size() == 2 &&
|
|
static_cast<X86Operand*>(Operands[1])->isMem()) {
|
|
delete Operands[0];
|
|
Operands[0] = X86Operand::CreateToken("sldtw", NameLoc);
|
|
}
|
|
|
|
|
|
// The assembler accepts these instructions with no operand as a synonym for
|
|
// an instruction acting on st(1). e.g. "fxch" -> "fxch %st(1)".
|
|
if ((Name == "fxch" || Name == "fucom" || Name == "fucomp" ||
|
|
Name == "faddp" || Name == "fsubp" || Name == "fsubrp" ||
|
|
Name == "fmulp" || Name == "fdivp" || Name == "fdivrp") &&
|
|
Operands.size() == 1) {
|
|
Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
|
|
NameLoc, NameLoc));
|
|
}
|
|
|
|
// The assembler accepts these instructions with two few operands as a synonym
|
|
// for taking %st(1),%st(0) or X, %st(0).
|
|
if ((Name == "fcomi" || Name == "fucomi" || Name == "fucompi" ||
|
|
Name == "fcompi" ) &&
|
|
Operands.size() < 3) {
|
|
if (Operands.size() == 1)
|
|
Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(1)"),
|
|
NameLoc, NameLoc));
|
|
Operands.push_back(X86Operand::CreateReg(MatchRegisterName("st(0)"),
|
|
NameLoc, NameLoc));
|
|
}
|
|
|
|
// The assembler accepts various amounts of brokenness for fnstsw.
|
|
if (Name == "fnstsw" || Name == "fnstsww") {
|
|
if (Operands.size() == 2 &&
|
|
static_cast<X86Operand*>(Operands[1])->isReg()) {
|
|
// "fnstsw al" and "fnstsw eax" -> "fnstw"
|
|
unsigned Reg = static_cast<X86Operand*>(Operands[1])->Reg.RegNo;
|
|
if (Reg == MatchRegisterName("eax") ||
|
|
Reg == MatchRegisterName("al")) {
|
|
delete Operands[1];
|
|
Operands.pop_back();
|
|
}
|
|
}
|
|
|
|
// "fnstw" -> "fnstw %ax"
|
|
if (Operands.size() == 1)
|
|
Operands.push_back(X86Operand::CreateReg(MatchRegisterName("ax"),
|
|
NameLoc, NameLoc));
|
|
}
|
|
|
|
// FIXME: Hack to handle recognize "aa[dm]" -> "aa[dm] $0xA".
|
|
if ((Name.startswith("aad") || Name.startswith("aam")) &&
|
|
Operands.size() == 1) {
|
|
const MCExpr *A = MCConstantExpr::Create(0xA, getParser().getContext());
|
|
Operands.push_back(X86Operand::CreateImm(A, NameLoc, NameLoc));
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
bool X86ATTAsmParser::
|
|
MatchAndEmitInstruction(SMLoc IDLoc,
|
|
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
|
|
MCStreamer &Out) {
|
|
assert(!Operands.empty() && "Unexpect empty operand list!");
|
|
X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
|
|
assert(Op->isToken() && "Leading operand should always be a mnemonic!");
|
|
|
|
// First, handle aliases that expand to multiple instructions.
|
|
// FIXME: This should be replaced with a real .td file alias mechanism.
|
|
if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" ||
|
|
Op->getToken() == "fstsww" || Op->getToken() == "fstcww" ||
|
|
Op->getToken() == "finit" || Op->getToken() == "fsave" ||
|
|
Op->getToken() == "fstenv" || Op->getToken() == "fclex") {
|
|
MCInst Inst;
|
|
Inst.setOpcode(X86::WAIT);
|
|
Out.EmitInstruction(Inst);
|
|
|
|
const char *Repl =
|
|
StringSwitch<const char*>(Op->getToken())
|
|
.Case("finit", "fninit")
|
|
.Case("fsave", "fnsave")
|
|
.Case("fstcw", "fnstcw")
|
|
.Case("fstcww", "fnstcw")
|
|
.Case("fstenv", "fnstenv")
|
|
.Case("fstsw", "fnstsw")
|
|
.Case("fstsww", "fnstsw")
|
|
.Case("fclex", "fnclex")
|
|
.Default(0);
|
|
assert(Repl && "Unknown wait-prefixed instruction");
|
|
delete Operands[0];
|
|
Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
|
|
}
|
|
|
|
bool WasOriginallyInvalidOperand = false;
|
|
unsigned OrigErrorInfo;
|
|
MCInst Inst;
|
|
|
|
// First, try a direct match.
|
|
switch (MatchInstructionImpl(Operands, Inst, OrigErrorInfo)) {
|
|
case Match_Success:
|
|
Out.EmitInstruction(Inst);
|
|
return false;
|
|
case Match_MissingFeature:
|
|
Error(IDLoc, "instruction requires a CPU feature not currently enabled");
|
|
return true;
|
|
case Match_InvalidOperand:
|
|
WasOriginallyInvalidOperand = true;
|
|
break;
|
|
case Match_MnemonicFail:
|
|
break;
|
|
}
|
|
|
|
// FIXME: Ideally, we would only attempt suffix matches for things which are
|
|
// valid prefixes, and we could just infer the right unambiguous
|
|
// type. However, that requires substantially more matcher support than the
|
|
// following hack.
|
|
|
|
// Change the operand to point to a temporary token.
|
|
StringRef Base = Op->getToken();
|
|
SmallString<16> Tmp;
|
|
Tmp += Base;
|
|
Tmp += ' ';
|
|
Op->setTokenValue(Tmp.str());
|
|
|
|
// If this instruction starts with an 'f', then it is a floating point stack
|
|
// instruction. These come in up to three forms for 32-bit, 64-bit, and
|
|
// 80-bit floating point, which use the suffixes s,l,t respectively.
|
|
//
|
|
// Otherwise, we assume that this may be an integer instruction, which comes
|
|
// in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
|
|
const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
|
|
|
|
// Check for the various suffix matches.
|
|
Tmp[Base.size()] = Suffixes[0];
|
|
unsigned ErrorInfoIgnore;
|
|
MatchResultTy Match1, Match2, Match3, Match4;
|
|
|
|
Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
|
|
Tmp[Base.size()] = Suffixes[1];
|
|
Match2 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
|
|
Tmp[Base.size()] = Suffixes[2];
|
|
Match3 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
|
|
Tmp[Base.size()] = Suffixes[3];
|
|
Match4 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
|
|
|
|
// Restore the old token.
|
|
Op->setTokenValue(Base);
|
|
|
|
// If exactly one matched, then we treat that as a successful match (and the
|
|
// instruction will already have been filled in correctly, since the failing
|
|
// matches won't have modified it).
|
|
unsigned NumSuccessfulMatches =
|
|
(Match1 == Match_Success) + (Match2 == Match_Success) +
|
|
(Match3 == Match_Success) + (Match4 == Match_Success);
|
|
if (NumSuccessfulMatches == 1) {
|
|
Out.EmitInstruction(Inst);
|
|
return false;
|
|
}
|
|
|
|
// Otherwise, the match failed, try to produce a decent error message.
|
|
|
|
// If we had multiple suffix matches, then identify this as an ambiguous
|
|
// match.
|
|
if (NumSuccessfulMatches > 1) {
|
|
char MatchChars[4];
|
|
unsigned NumMatches = 0;
|
|
if (Match1 == Match_Success) MatchChars[NumMatches++] = Suffixes[0];
|
|
if (Match2 == Match_Success) MatchChars[NumMatches++] = Suffixes[1];
|
|
if (Match3 == Match_Success) MatchChars[NumMatches++] = Suffixes[2];
|
|
if (Match4 == Match_Success) MatchChars[NumMatches++] = Suffixes[3];
|
|
|
|
SmallString<126> Msg;
|
|
raw_svector_ostream OS(Msg);
|
|
OS << "ambiguous instructions require an explicit suffix (could be ";
|
|
for (unsigned i = 0; i != NumMatches; ++i) {
|
|
if (i != 0)
|
|
OS << ", ";
|
|
if (i + 1 == NumMatches)
|
|
OS << "or ";
|
|
OS << "'" << Base << MatchChars[i] << "'";
|
|
}
|
|
OS << ")";
|
|
Error(IDLoc, OS.str());
|
|
return true;
|
|
}
|
|
|
|
// Okay, we know that none of the variants matched successfully.
|
|
|
|
// If all of the instructions reported an invalid mnemonic, then the original
|
|
// mnemonic was invalid.
|
|
if ((Match1 == Match_MnemonicFail) && (Match2 == Match_MnemonicFail) &&
|
|
(Match3 == Match_MnemonicFail) && (Match4 == Match_MnemonicFail)) {
|
|
if (!WasOriginallyInvalidOperand) {
|
|
Error(IDLoc, "invalid instruction mnemonic '" + Base + "'");
|
|
return true;
|
|
}
|
|
|
|
// Recover location info for the operand if we know which was the problem.
|
|
SMLoc ErrorLoc = IDLoc;
|
|
if (OrigErrorInfo != ~0U) {
|
|
if (OrigErrorInfo >= Operands.size())
|
|
return Error(IDLoc, "too few operands for instruction");
|
|
|
|
ErrorLoc = ((X86Operand*)Operands[OrigErrorInfo])->getStartLoc();
|
|
if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
|
|
}
|
|
|
|
return Error(ErrorLoc, "invalid operand for instruction");
|
|
}
|
|
|
|
// If one instruction matched with a missing feature, report this as a
|
|
// missing feature.
|
|
if ((Match1 == Match_MissingFeature) + (Match2 == Match_MissingFeature) +
|
|
(Match3 == Match_MissingFeature) + (Match4 == Match_MissingFeature) == 1){
|
|
Error(IDLoc, "instruction requires a CPU feature not currently enabled");
|
|
return true;
|
|
}
|
|
|
|
// If one instruction matched with an invalid operand, report this as an
|
|
// operand failure.
|
|
if ((Match1 == Match_InvalidOperand) + (Match2 == Match_InvalidOperand) +
|
|
(Match3 == Match_InvalidOperand) + (Match4 == Match_InvalidOperand) == 1){
|
|
Error(IDLoc, "invalid operand for instruction");
|
|
return true;
|
|
}
|
|
|
|
// If all of these were an outright failure, report it in a useless way.
|
|
// FIXME: We should give nicer diagnostics about the exact failure.
|
|
Error(IDLoc, "unknown use of instruction mnemonic without a size suffix");
|
|
return true;
|
|
}
|
|
|
|
|
|
bool X86ATTAsmParser::ParseDirective(AsmToken DirectiveID) {
|
|
StringRef IDVal = DirectiveID.getIdentifier();
|
|
if (IDVal == ".word")
|
|
return ParseDirectiveWord(2, DirectiveID.getLoc());
|
|
return true;
|
|
}
|
|
|
|
/// ParseDirectiveWord
|
|
/// ::= .word [ expression (, expression)* ]
|
|
bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
|
|
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
for (;;) {
|
|
const MCExpr *Value;
|
|
if (getParser().ParseExpression(Value))
|
|
return true;
|
|
|
|
getParser().getStreamer().EmitValue(Value, Size, 0 /*addrspace*/);
|
|
|
|
if (getLexer().is(AsmToken::EndOfStatement))
|
|
break;
|
|
|
|
// FIXME: Improve diagnostic.
|
|
if (getLexer().isNot(AsmToken::Comma))
|
|
return Error(L, "unexpected token in directive");
|
|
Parser.Lex();
|
|
}
|
|
}
|
|
|
|
Parser.Lex();
|
|
return false;
|
|
}
|
|
|
|
|
|
|
|
|
|
extern "C" void LLVMInitializeX86AsmLexer();
|
|
|
|
// Force static initialization.
|
|
extern "C" void LLVMInitializeX86AsmParser() {
|
|
RegisterAsmParser<X86_32ATTAsmParser> X(TheX86_32Target);
|
|
RegisterAsmParser<X86_64ATTAsmParser> Y(TheX86_64Target);
|
|
LLVMInitializeX86AsmLexer();
|
|
}
|
|
|
|
#define GET_REGISTER_MATCHER
|
|
#define GET_MATCHER_IMPLEMENTATION
|
|
#include "X86GenAsmMatcher.inc"
|