Jakob Stoklund Olesen fb9ebbf236 Switch most getReservedRegs() clients to the MRI equivalent. ... Using the cached bit vector in MRI avoids comstantly allocating and recomputing the reserved register bit vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165983 91177308-0d34-0410-b5e6-96231b3b80d8		2012-10-15 21:57:41 +00:00
..
Analysis	Resubmit the changes to llvm core to update the functions to support different pointer sizes on a per address space basis.	2012-10-15 16:24:29 +00:00
Archive
AsmParser	Move the Attributes::Builder outside of the Attributes class and into its own class named AttrBuilder. No functionality change.	2012-10-15 20:35:56 +00:00
Bitcode	Move the Attributes::Builder outside of the Attributes class and into its own class named AttrBuilder. No functionality change.	2012-10-15 20:35:56 +00:00
CodeGen	Switch most getReservedRegs() clients to the MRI equivalent.	2012-10-15 21:57:41 +00:00
DebugInfo
ExecutionEngine	Resubmit the changes to llvm core to update the functions to support different pointer sizes on a per address space basis.	2012-10-15 16:24:29 +00:00
Linker
MC	[ms-inline asm] If we parsed a statement and the opcode is valid, then it's an instruction.	2012-10-15 19:08:18 +00:00
Object
Support
TableGen
Target	ARM: v1i64 and v2i64 VBSL intrinsic support.	2012-10-15 21:23:40 +00:00
Transforms	Move the Attributes::Builder outside of the Attributes class and into its own class named AttrBuilder. No functionality change.	2012-10-15 20:35:56 +00:00
VMCore	Move the Attributes::Builder outside of the Attributes class and into its own class named AttrBuilder. No functionality change.	2012-10-15 20:35:56 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile