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cba9d1273a
ADDSUBPD nodes out of blends of adds and subs. This allows us to actually form these instructions with SSE3 rather than only forming them when we had both SSE3 for the ADDSUB instructions and SSE4.1 for the blend instructions. ;] Kind-of important. I've adjusted the CPU requirements on one of the tests to demonstrate this kicking in nicely for an SSE3 cpu configuration. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217848 91177308-0d34-0410-b5e6-96231b3b80d8
144 lines
4.0 KiB
LLVM
144 lines
4.0 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=core2 | FileCheck %s -check-prefix=SSE -check-prefix=CHECK
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; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx | FileCheck %s -check-prefix=AVX -check-prefix=CHECK
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; Test ADDSUB ISel patterns.
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; Functions below are obtained from the following source:
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;
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; typedef double double2 __attribute__((ext_vector_type(2)));
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; typedef double double4 __attribute__((ext_vector_type(4)));
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; typedef float float4 __attribute__((ext_vector_type(4)));
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; typedef float float8 __attribute__((ext_vector_type(8)));
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;
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; float4 test1(float4 A, float4 B) {
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; float4 X = A - B;
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; float4 Y = A + B;
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; return (float4){X[0], Y[1], X[2], Y[3]};
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; }
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;
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; float8 test2(float8 A, float8 B) {
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; float8 X = A - B;
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; float8 Y = A + B;
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; return (float8){X[0], Y[1], X[2], Y[3], X[4], Y[5], X[6], Y[7]};
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; }
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;
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; double4 test3(double4 A, double4 B) {
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; double4 X = A - B;
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; double4 Y = A + B;
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; return (double4){X[0], Y[1], X[2], Y[3]};
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; }
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;
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; double2 test4(double2 A, double2 B) {
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; double2 X = A - B;
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; double2 Y = A + B;
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; return (double2){X[0], Y[1]};
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; }
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define <4 x float> @test1(<4 x float> %A, <4 x float> %B) {
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%sub = fsub <4 x float> %A, %B
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%add = fadd <4 x float> %A, %B
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%vecinit6 = shufflevector <4 x float> %sub, <4 x float> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x float> %vecinit6
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}
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; CHECK-LABEL: test1
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; SSE: addsubps
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; AVX: vaddsubps
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; CHECK-NEXT: ret
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define <8 x float> @test2(<8 x float> %A, <8 x float> %B) {
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%sub = fsub <8 x float> %A, %B
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%add = fadd <8 x float> %A, %B
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%vecinit14 = shufflevector <8 x float> %sub, <8 x float> %add, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
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ret <8 x float> %vecinit14
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}
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; CHECK-LABEL: test2
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; SSE: addsubps
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; SSE-NEXT: addsubps
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; AVX: vaddsubps
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; AVX-NOT: vaddsubps
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; CHECK: ret
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define <4 x double> @test3(<4 x double> %A, <4 x double> %B) {
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%sub = fsub <4 x double> %A, %B
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%add = fadd <4 x double> %A, %B
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%vecinit6 = shufflevector <4 x double> %sub, <4 x double> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x double> %vecinit6
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}
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; CHECK-LABEL: test3
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; SSE: addsubpd
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; SSE: addsubpd
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; AVX: vaddsubpd
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; AVX-NOT: vaddsubpd
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; CHECK: ret
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define <2 x double> @test4(<2 x double> %A, <2 x double> %B) #0 {
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%add = fadd <2 x double> %A, %B
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%sub = fsub <2 x double> %A, %B
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%vecinit2 = shufflevector <2 x double> %sub, <2 x double> %add, <2 x i32> <i32 0, i32 3>
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ret <2 x double> %vecinit2
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}
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; CHECK-LABEL: test4
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; SSE: addsubpd
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; AVX: vaddsubpd
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; CHECK-NEXT: ret
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define <4 x float> @test1b(<4 x float> %A, <4 x float>* %B) {
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%1 = load <4 x float>* %B
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%add = fadd <4 x float> %A, %1
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%sub = fsub <4 x float> %A, %1
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%vecinit6 = shufflevector <4 x float> %sub, <4 x float> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x float> %vecinit6
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}
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; CHECK-LABEL: test1b
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; SSE: addsubps
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; AVX: vaddsubps
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; CHECK-NEXT: ret
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define <8 x float> @test2b(<8 x float> %A, <8 x float>* %B) {
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%1 = load <8 x float>* %B
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%add = fadd <8 x float> %A, %1
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%sub = fsub <8 x float> %A, %1
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%vecinit14 = shufflevector <8 x float> %sub, <8 x float> %add, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
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ret <8 x float> %vecinit14
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}
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; CHECK-LABEL: test2b
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; SSE: addsubps
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; SSE-NEXT: addsubps
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; AVX: vaddsubps
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; AVX-NOT: vaddsubps
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; CHECK: ret
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define <4 x double> @test3b(<4 x double> %A, <4 x double>* %B) {
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%1 = load <4 x double>* %B
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%add = fadd <4 x double> %A, %1
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%sub = fsub <4 x double> %A, %1
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%vecinit6 = shufflevector <4 x double> %sub, <4 x double> %add, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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ret <4 x double> %vecinit6
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}
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; CHECK-LABEL: test3b
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; SSE: addsubpd
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; SSE: addsubpd
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; AVX: vaddsubpd
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; AVX-NOT: vaddsubpd
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; CHECK: ret
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define <2 x double> @test4b(<2 x double> %A, <2 x double>* %B) {
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%1 = load <2 x double>* %B
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%sub = fsub <2 x double> %A, %1
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%add = fadd <2 x double> %A, %1
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%vecinit2 = shufflevector <2 x double> %sub, <2 x double> %add, <2 x i32> <i32 0, i32 3>
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ret <2 x double> %vecinit2
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}
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; CHECK-LABEL: test4b
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; SSE: addsubpd
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; AVX: vaddsubpd
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; CHECK-NEXT: ret
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