mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Summary: No functional change yet, it's just an object replacement for an enum. It will allow us to gather ABI information in a single place so that we can start testing for properties of the ABI's instead of the ABI itself. For example we will eventually be able to use: ABI.MinStackAlignmentInBytes() instead of: (isABI_N32() || isABI_N64()) ? 16 : 8 which is clearer and more maintainable. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3341 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220568 91177308-0d34-0410-b5e6-96231b3b80d8
1037 lines
34 KiB
C++
1037 lines
34 KiB
C++
//===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to GAS-format MIPS assembly language.
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//
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//===----------------------------------------------------------------------===//
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#include "InstPrinter/MipsInstPrinter.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "MCTargetDesc/MipsMCNaCl.h"
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#include "Mips.h"
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#include "MipsAsmPrinter.h"
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#include "MipsInstrInfo.h"
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#include "MipsMCInstLower.h"
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#include "MipsTargetStreamer.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/IR/BasicBlock.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/InlineAsm.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Mangler.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCELFStreamer.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCSection.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/ELF.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetLoweringObjectFile.h"
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#include "llvm/Target/TargetOptions.h"
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#include <string>
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using namespace llvm;
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#define DEBUG_TYPE "mips-asm-printer"
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MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() {
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return static_cast<MipsTargetStreamer &>(*OutStreamer.getTargetStreamer());
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}
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bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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Subtarget = &TM.getSubtarget<MipsSubtarget>();
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// Initialize TargetLoweringObjectFile.
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const_cast<TargetLoweringObjectFile &>(getObjFileLowering())
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.Initialize(OutContext, TM);
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MipsFI = MF.getInfo<MipsFunctionInfo>();
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if (Subtarget->inMips16Mode())
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for (std::map<
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const char *,
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const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
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it = MipsFI->StubsNeeded.begin();
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it != MipsFI->StubsNeeded.end(); ++it) {
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const char *Symbol = it->first;
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const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
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if (StubsNeeded.find(Symbol) == StubsNeeded.end())
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StubsNeeded[Symbol] = Signature;
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}
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MCP = MF.getConstantPool();
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// In NaCl, all indirect jump targets must be aligned to bundle size.
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if (Subtarget->isTargetNaCl())
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NaClAlignIndirectJumpTargets(MF);
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AsmPrinter::runOnMachineFunction(MF);
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return true;
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}
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bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
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MCOp = MCInstLowering.LowerOperand(MO);
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return MCOp.isValid();
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}
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#include "MipsGenMCPseudoLowering.inc"
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// Lower PseudoReturn/PseudoIndirectBranch/PseudoIndirectBranch64 to JR, JR_MM,
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// JALR, or JALR64 as appropriate for the target
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void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer,
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const MachineInstr *MI) {
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bool HasLinkReg = false;
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MCInst TmpInst0;
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if (Subtarget->hasMips64r6()) {
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// MIPS64r6 should use (JALR64 ZERO_64, $rs)
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TmpInst0.setOpcode(Mips::JALR64);
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HasLinkReg = true;
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} else if (Subtarget->hasMips32r6()) {
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// MIPS32r6 should use (JALR ZERO, $rs)
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TmpInst0.setOpcode(Mips::JALR);
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HasLinkReg = true;
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} else if (Subtarget->inMicroMipsMode())
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// microMIPS should use (JR_MM $rs)
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TmpInst0.setOpcode(Mips::JR_MM);
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else {
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// Everything else should use (JR $rs)
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TmpInst0.setOpcode(Mips::JR);
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}
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MCOperand MCOp;
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if (HasLinkReg) {
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unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
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TmpInst0.addOperand(MCOperand::CreateReg(ZeroReg));
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}
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lowerOperand(MI->getOperand(0), MCOp);
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TmpInst0.addOperand(MCOp);
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EmitToStreamer(OutStreamer, TmpInst0);
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}
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void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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MipsTargetStreamer &TS = getTargetStreamer();
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TS.forbidModuleDirective();
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if (MI->isDebugValue()) {
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SmallString<128> Str;
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raw_svector_ostream OS(Str);
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PrintDebugValueComment(MI, OS);
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return;
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}
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// If we just ended a constant pool, mark it as such.
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if (InConstantPool && MI->getOpcode() != Mips::CONSTPOOL_ENTRY) {
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OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
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InConstantPool = false;
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}
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if (MI->getOpcode() == Mips::CONSTPOOL_ENTRY) {
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// CONSTPOOL_ENTRY - This instruction represents a floating
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//constant pool in the function. The first operand is the ID#
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// for this instruction, the second is the index into the
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// MachineConstantPool that this is, the third is the size in
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// bytes of this constant pool entry.
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// The required alignment is specified on the basic block holding this MI.
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//
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unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
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unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
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// If this is the first entry of the pool, mark it.
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if (!InConstantPool) {
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OutStreamer.EmitDataRegion(MCDR_DataRegion);
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InConstantPool = true;
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}
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OutStreamer.EmitLabel(GetCPISymbol(LabelId));
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const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
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if (MCPE.isMachineConstantPoolEntry())
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EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
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else
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EmitGlobalConstant(MCPE.Val.ConstVal);
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return;
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}
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MachineBasicBlock::const_instr_iterator I = MI;
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MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
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do {
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// Do any auto-generated pseudo lowerings.
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if (emitPseudoExpansionLowering(OutStreamer, &*I))
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continue;
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if (I->getOpcode() == Mips::PseudoReturn ||
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I->getOpcode() == Mips::PseudoReturn64 ||
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I->getOpcode() == Mips::PseudoIndirectBranch ||
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I->getOpcode() == Mips::PseudoIndirectBranch64) {
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emitPseudoIndirectBranch(OutStreamer, &*I);
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continue;
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}
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// The inMips16Mode() test is not permanent.
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// Some instructions are marked as pseudo right now which
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// would make the test fail for the wrong reason but
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// that will be fixed soon. We need this here because we are
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// removing another test for this situation downstream in the
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// callchain.
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//
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if (I->isPseudo() && !Subtarget->inMips16Mode()
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&& !isLongBranchPseudo(I->getOpcode()))
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llvm_unreachable("Pseudo opcode found in EmitInstruction()");
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MCInst TmpInst0;
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MCInstLowering.Lower(I, TmpInst0);
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EmitToStreamer(OutStreamer, TmpInst0);
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} while ((++I != E) && I->isInsideBundle()); // Delay slot check
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}
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//===----------------------------------------------------------------------===//
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//
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// Mips Asm Directives
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//
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// -- Frame directive "frame Stackpointer, Stacksize, RARegister"
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// Describe the stack frame.
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//
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// -- Mask directives "(f)mask bitmask, offset"
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// Tells the assembler which registers are saved and where.
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// bitmask - contain a little endian bitset indicating which registers are
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// saved on function prologue (e.g. with a 0x80000000 mask, the
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// assembler knows the register 31 (RA) is saved at prologue.
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// offset - the position before stack pointer subtraction indicating where
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// the first saved register on prologue is located. (e.g. with a
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//
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// Consider the following function prologue:
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//
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// .frame $fp,48,$ra
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// .mask 0xc0000000,-8
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// addiu $sp, $sp, -48
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// sw $ra, 40($sp)
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// sw $fp, 36($sp)
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//
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// With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
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// 30 (FP) are saved at prologue. As the save order on prologue is from
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// left to right, RA is saved first. A -8 offset means that after the
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// stack pointer subtration, the first register in the mask (RA) will be
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// saved at address 48-8=40.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Mask directives
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//===----------------------------------------------------------------------===//
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// Create a bitmask with all callee saved registers for CPU or Floating Point
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// registers. For CPU registers consider RA, GP and FP for saving if necessary.
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void MipsAsmPrinter::printSavedRegsBitmask() {
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// CPU and FPU Saved Registers Bitmasks
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unsigned CPUBitmask = 0, FPUBitmask = 0;
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int CPUTopSavedRegOff, FPUTopSavedRegOff;
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// Set the CPU and FPU Bitmasks
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const MachineFrameInfo *MFI = MF->getFrameInfo();
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const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
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// size of stack area to which FP callee-saved regs are saved.
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unsigned CPURegSize = Mips::GPR32RegClass.getSize();
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unsigned FGR32RegSize = Mips::FGR32RegClass.getSize();
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unsigned AFGR64RegSize = Mips::AFGR64RegClass.getSize();
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bool HasAFGR64Reg = false;
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unsigned CSFPRegsSize = 0;
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unsigned i, e = CSI.size();
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// Set FPU Bitmask.
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for (i = 0; i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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if (Mips::GPR32RegClass.contains(Reg))
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break;
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unsigned RegNum =
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TM.getSubtargetImpl()->getRegisterInfo()->getEncodingValue(Reg);
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if (Mips::AFGR64RegClass.contains(Reg)) {
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FPUBitmask |= (3 << RegNum);
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CSFPRegsSize += AFGR64RegSize;
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HasAFGR64Reg = true;
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continue;
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}
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FPUBitmask |= (1 << RegNum);
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CSFPRegsSize += FGR32RegSize;
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}
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// Set CPU Bitmask.
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for (; i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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unsigned RegNum =
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TM.getSubtargetImpl()->getRegisterInfo()->getEncodingValue(Reg);
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CPUBitmask |= (1 << RegNum);
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}
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// FP Regs are saved right below where the virtual frame pointer points to.
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FPUTopSavedRegOff = FPUBitmask ?
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(HasAFGR64Reg ? -AFGR64RegSize : -FGR32RegSize) : 0;
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// CPU Regs are saved below FP Regs.
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CPUTopSavedRegOff = CPUBitmask ? -CSFPRegsSize - CPURegSize : 0;
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MipsTargetStreamer &TS = getTargetStreamer();
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// Print CPUBitmask
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TS.emitMask(CPUBitmask, CPUTopSavedRegOff);
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// Print FPUBitmask
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TS.emitFMask(FPUBitmask, FPUTopSavedRegOff);
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}
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//===----------------------------------------------------------------------===//
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// Frame and Set directives
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//===----------------------------------------------------------------------===//
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/// Frame Directive
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void MipsAsmPrinter::emitFrameDirective() {
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const TargetRegisterInfo &RI = *TM.getSubtargetImpl()->getRegisterInfo();
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unsigned stackReg = RI.getFrameRegister(*MF);
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unsigned returnReg = RI.getRARegister();
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unsigned stackSize = MF->getFrameInfo()->getStackSize();
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getTargetStreamer().emitFrame(stackReg, stackSize, returnReg);
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}
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/// Emit Set directives.
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const char *MipsAsmPrinter::getCurrentABIString() const {
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switch (Subtarget->getABI().GetEnumValue()) {
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case MipsABIInfo::ABI::O32: return "abi32";
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case MipsABIInfo::ABI::N32: return "abiN32";
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case MipsABIInfo::ABI::N64: return "abi64";
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case MipsABIInfo::ABI::EABI: return "eabi32"; // TODO: handle eabi64
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default: llvm_unreachable("Unknown Mips ABI");
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}
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}
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void MipsAsmPrinter::EmitFunctionEntryLabel() {
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MipsTargetStreamer &TS = getTargetStreamer();
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// NaCl sandboxing requires that indirect call instructions are masked.
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// This means that function entry points should be bundle-aligned.
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if (Subtarget->isTargetNaCl())
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EmitAlignment(std::max(MF->getAlignment(), MIPS_NACL_BUNDLE_ALIGN));
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if (Subtarget->inMicroMipsMode())
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TS.emitDirectiveSetMicroMips();
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else
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TS.emitDirectiveSetNoMicroMips();
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if (Subtarget->inMips16Mode())
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TS.emitDirectiveSetMips16();
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else
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TS.emitDirectiveSetNoMips16();
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TS.emitDirectiveEnt(*CurrentFnSym);
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OutStreamer.EmitLabel(CurrentFnSym);
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}
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/// EmitFunctionBodyStart - Targets can override this to emit stuff before
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/// the first basic block in the function.
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void MipsAsmPrinter::EmitFunctionBodyStart() {
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MipsTargetStreamer &TS = getTargetStreamer();
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MCInstLowering.Initialize(&MF->getContext());
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bool IsNakedFunction =
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MF->getFunction()->
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getAttributes().hasAttribute(AttributeSet::FunctionIndex,
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Attribute::Naked);
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if (!IsNakedFunction)
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emitFrameDirective();
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if (!IsNakedFunction)
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printSavedRegsBitmask();
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if (!Subtarget->inMips16Mode()) {
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TS.emitDirectiveSetNoReorder();
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TS.emitDirectiveSetNoMacro();
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TS.emitDirectiveSetNoAt();
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}
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}
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/// EmitFunctionBodyEnd - Targets can override this to emit stuff after
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/// the last basic block in the function.
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void MipsAsmPrinter::EmitFunctionBodyEnd() {
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MipsTargetStreamer &TS = getTargetStreamer();
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// There are instruction for this macros, but they must
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// always be at the function end, and we can't emit and
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// break with BB logic.
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if (!Subtarget->inMips16Mode()) {
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TS.emitDirectiveSetAt();
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TS.emitDirectiveSetMacro();
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TS.emitDirectiveSetReorder();
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}
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TS.emitDirectiveEnd(CurrentFnSym->getName());
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// Make sure to terminate any constant pools that were at the end
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// of the function.
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if (!InConstantPool)
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return;
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InConstantPool = false;
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OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
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}
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/// isBlockOnlyReachableByFallthough - Return true if the basic block has
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/// exactly one predecessor and the control transfer mechanism between
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/// the predecessor and this block is a fall-through.
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bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock*
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MBB) const {
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// The predecessor has to be immediately before this block.
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const MachineBasicBlock *Pred = *MBB->pred_begin();
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// If the predecessor is a switch statement, assume a jump table
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// implementation, so it is not a fall through.
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if (const BasicBlock *bb = Pred->getBasicBlock())
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if (isa<SwitchInst>(bb->getTerminator()))
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return false;
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// If this is a landing pad, it isn't a fall through. If it has no preds,
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// then nothing falls through to it.
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if (MBB->isLandingPad() || MBB->pred_empty())
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return false;
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// If there isn't exactly one predecessor, it can't be a fall through.
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MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), PI2 = PI;
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++PI2;
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if (PI2 != MBB->pred_end())
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return false;
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// The predecessor has to be immediately before this block.
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if (!Pred->isLayoutSuccessor(MBB))
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return false;
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// If the block is completely empty, then it definitely does fall through.
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if (Pred->empty())
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return true;
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// Otherwise, check the last instruction.
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// Check if the last terminator is an unconditional branch.
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MachineBasicBlock::const_iterator I = Pred->end();
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while (I != Pred->begin() && !(--I)->isTerminator()) ;
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return !I->isBarrier();
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}
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// Print out an operand for an inline asm expression.
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bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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unsigned AsmVariant,const char *ExtraCode,
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raw_ostream &O) {
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// Does this asm operand have a single letter operand modifier?
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if (ExtraCode && ExtraCode[0]) {
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if (ExtraCode[1] != 0) return true; // Unknown modifier.
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const MachineOperand &MO = MI->getOperand(OpNum);
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switch (ExtraCode[0]) {
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default:
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// See if this is a generic print operand
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return AsmPrinter::PrintAsmOperand(MI,OpNum,AsmVariant,ExtraCode,O);
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case 'X': // hex const int
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if ((MO.getType()) != MachineOperand::MO_Immediate)
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return true;
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O << "0x" << StringRef(utohexstr(MO.getImm())).lower();
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return false;
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case 'x': // hex const int (low 16 bits)
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if ((MO.getType()) != MachineOperand::MO_Immediate)
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return true;
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O << "0x" << StringRef(utohexstr(MO.getImm() & 0xffff)).lower();
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return false;
|
|
case 'd': // decimal const int
|
|
if ((MO.getType()) != MachineOperand::MO_Immediate)
|
|
return true;
|
|
O << MO.getImm();
|
|
return false;
|
|
case 'm': // decimal const int minus 1
|
|
if ((MO.getType()) != MachineOperand::MO_Immediate)
|
|
return true;
|
|
O << MO.getImm() - 1;
|
|
return false;
|
|
case 'z': {
|
|
// $0 if zero, regular printing otherwise
|
|
if (MO.getType() != MachineOperand::MO_Immediate)
|
|
return true;
|
|
int64_t Val = MO.getImm();
|
|
if (Val)
|
|
O << Val;
|
|
else
|
|
O << "$0";
|
|
return false;
|
|
}
|
|
case 'D': // Second part of a double word register operand
|
|
case 'L': // Low order register of a double word register operand
|
|
case 'M': // High order register of a double word register operand
|
|
{
|
|
if (OpNum == 0)
|
|
return true;
|
|
const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
|
|
if (!FlagsOP.isImm())
|
|
return true;
|
|
unsigned Flags = FlagsOP.getImm();
|
|
unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
|
|
// Number of registers represented by this operand. We are looking
|
|
// for 2 for 32 bit mode and 1 for 64 bit mode.
|
|
if (NumVals != 2) {
|
|
if (Subtarget->isGP64bit() && NumVals == 1 && MO.isReg()) {
|
|
unsigned Reg = MO.getReg();
|
|
O << '$' << MipsInstPrinter::getRegisterName(Reg);
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
unsigned RegOp = OpNum;
|
|
if (!Subtarget->isGP64bit()){
|
|
// Endianess reverses which register holds the high or low value
|
|
// between M and L.
|
|
switch(ExtraCode[0]) {
|
|
case 'M':
|
|
RegOp = (Subtarget->isLittle()) ? OpNum + 1 : OpNum;
|
|
break;
|
|
case 'L':
|
|
RegOp = (Subtarget->isLittle()) ? OpNum : OpNum + 1;
|
|
break;
|
|
case 'D': // Always the second part
|
|
RegOp = OpNum + 1;
|
|
}
|
|
if (RegOp >= MI->getNumOperands())
|
|
return true;
|
|
const MachineOperand &MO = MI->getOperand(RegOp);
|
|
if (!MO.isReg())
|
|
return true;
|
|
unsigned Reg = MO.getReg();
|
|
O << '$' << MipsInstPrinter::getRegisterName(Reg);
|
|
return false;
|
|
}
|
|
}
|
|
case 'w':
|
|
// Print MSA registers for the 'f' constraint
|
|
// In LLVM, the 'w' modifier doesn't need to do anything.
|
|
// We can just call printOperand as normal.
|
|
break;
|
|
}
|
|
}
|
|
|
|
printOperand(MI, OpNum, O);
|
|
return false;
|
|
}
|
|
|
|
bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
|
|
unsigned OpNum, unsigned AsmVariant,
|
|
const char *ExtraCode,
|
|
raw_ostream &O) {
|
|
int Offset = 0;
|
|
// Currently we are expecting either no ExtraCode or 'D'
|
|
if (ExtraCode) {
|
|
if (ExtraCode[0] == 'D')
|
|
Offset = 4;
|
|
else
|
|
return true; // Unknown modifier.
|
|
}
|
|
|
|
const MachineOperand &MO = MI->getOperand(OpNum);
|
|
assert(MO.isReg() && "unexpected inline asm memory operand");
|
|
O << Offset << "($" << MipsInstPrinter::getRegisterName(MO.getReg()) << ")";
|
|
|
|
return false;
|
|
}
|
|
|
|
void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
|
|
raw_ostream &O) {
|
|
const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
|
|
const MachineOperand &MO = MI->getOperand(opNum);
|
|
bool closeP = false;
|
|
|
|
if (MO.getTargetFlags())
|
|
closeP = true;
|
|
|
|
switch(MO.getTargetFlags()) {
|
|
case MipsII::MO_GPREL: O << "%gp_rel("; break;
|
|
case MipsII::MO_GOT_CALL: O << "%call16("; break;
|
|
case MipsII::MO_GOT: O << "%got("; break;
|
|
case MipsII::MO_ABS_HI: O << "%hi("; break;
|
|
case MipsII::MO_ABS_LO: O << "%lo("; break;
|
|
case MipsII::MO_TLSGD: O << "%tlsgd("; break;
|
|
case MipsII::MO_GOTTPREL: O << "%gottprel("; break;
|
|
case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break;
|
|
case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break;
|
|
case MipsII::MO_GPOFF_HI: O << "%hi(%neg(%gp_rel("; break;
|
|
case MipsII::MO_GPOFF_LO: O << "%lo(%neg(%gp_rel("; break;
|
|
case MipsII::MO_GOT_DISP: O << "%got_disp("; break;
|
|
case MipsII::MO_GOT_PAGE: O << "%got_page("; break;
|
|
case MipsII::MO_GOT_OFST: O << "%got_ofst("; break;
|
|
}
|
|
|
|
switch (MO.getType()) {
|
|
case MachineOperand::MO_Register:
|
|
O << '$'
|
|
<< StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
|
|
break;
|
|
|
|
case MachineOperand::MO_Immediate:
|
|
O << MO.getImm();
|
|
break;
|
|
|
|
case MachineOperand::MO_MachineBasicBlock:
|
|
O << *MO.getMBB()->getSymbol();
|
|
return;
|
|
|
|
case MachineOperand::MO_GlobalAddress:
|
|
O << *getSymbol(MO.getGlobal());
|
|
break;
|
|
|
|
case MachineOperand::MO_BlockAddress: {
|
|
MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
|
|
O << BA->getName();
|
|
break;
|
|
}
|
|
|
|
case MachineOperand::MO_ConstantPoolIndex:
|
|
O << DL->getPrivateGlobalPrefix() << "CPI"
|
|
<< getFunctionNumber() << "_" << MO.getIndex();
|
|
if (MO.getOffset())
|
|
O << "+" << MO.getOffset();
|
|
break;
|
|
|
|
default:
|
|
llvm_unreachable("<unknown operand type>");
|
|
}
|
|
|
|
if (closeP) O << ")";
|
|
}
|
|
|
|
void MipsAsmPrinter::printUnsignedImm(const MachineInstr *MI, int opNum,
|
|
raw_ostream &O) {
|
|
const MachineOperand &MO = MI->getOperand(opNum);
|
|
if (MO.isImm())
|
|
O << (unsigned short int)MO.getImm();
|
|
else
|
|
printOperand(MI, opNum, O);
|
|
}
|
|
|
|
void MipsAsmPrinter::printUnsignedImm8(const MachineInstr *MI, int opNum,
|
|
raw_ostream &O) {
|
|
const MachineOperand &MO = MI->getOperand(opNum);
|
|
if (MO.isImm())
|
|
O << (unsigned short int)(unsigned char)MO.getImm();
|
|
else
|
|
printOperand(MI, opNum, O);
|
|
}
|
|
|
|
void MipsAsmPrinter::
|
|
printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) {
|
|
// Load/Store memory operands -- imm($reg)
|
|
// If PIC target the target is loaded as the
|
|
// pattern lw $25,%call16($28)
|
|
printOperand(MI, opNum+1, O);
|
|
O << "(";
|
|
printOperand(MI, opNum, O);
|
|
O << ")";
|
|
}
|
|
|
|
void MipsAsmPrinter::
|
|
printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O) {
|
|
// when using stack locations for not load/store instructions
|
|
// print the same way as all normal 3 operand instructions.
|
|
printOperand(MI, opNum, O);
|
|
O << ", ";
|
|
printOperand(MI, opNum+1, O);
|
|
return;
|
|
}
|
|
|
|
void MipsAsmPrinter::
|
|
printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
|
|
const char *Modifier) {
|
|
const MachineOperand &MO = MI->getOperand(opNum);
|
|
O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
|
|
}
|
|
|
|
void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
|
|
bool IsABICalls = Subtarget->isABICalls();
|
|
if (IsABICalls) {
|
|
getTargetStreamer().emitDirectiveAbiCalls();
|
|
Reloc::Model RM = TM.getRelocationModel();
|
|
// FIXME: This condition should be a lot more complicated that it is here.
|
|
// Ideally it should test for properties of the ABI and not the ABI
|
|
// itself.
|
|
// For the moment, I'm only correcting enough to make MIPS-IV work.
|
|
if (RM == Reloc::Static && !Subtarget->isABI_N64())
|
|
getTargetStreamer().emitDirectiveOptionPic0();
|
|
}
|
|
|
|
// Tell the assembler which ABI we are using
|
|
std::string SectionName = std::string(".mdebug.") + getCurrentABIString();
|
|
OutStreamer.SwitchSection(OutContext.getELFSection(
|
|
SectionName, ELF::SHT_PROGBITS, 0, SectionKind::getDataRel()));
|
|
|
|
// NaN: At the moment we only support:
|
|
// 1. .nan legacy (default)
|
|
// 2. .nan 2008
|
|
Subtarget->isNaN2008() ? getTargetStreamer().emitDirectiveNaN2008()
|
|
: getTargetStreamer().emitDirectiveNaNLegacy();
|
|
|
|
// TODO: handle O64 ABI
|
|
|
|
if (Subtarget->isABI_EABI()) {
|
|
if (Subtarget->isGP32bit())
|
|
OutStreamer.SwitchSection(
|
|
OutContext.getELFSection(".gcc_compiled_long32", ELF::SHT_PROGBITS, 0,
|
|
SectionKind::getDataRel()));
|
|
else
|
|
OutStreamer.SwitchSection(
|
|
OutContext.getELFSection(".gcc_compiled_long64", ELF::SHT_PROGBITS, 0,
|
|
SectionKind::getDataRel()));
|
|
}
|
|
|
|
getTargetStreamer().updateABIInfo(*Subtarget);
|
|
|
|
// We should always emit a '.module fp=...' but binutils 2.24 does not accept
|
|
// it. We therefore emit it when it contradicts the ABI defaults (-mfpxx or
|
|
// -mfp64) and omit it otherwise.
|
|
if (Subtarget->isABI_O32() && (Subtarget->isABI_FPXX() ||
|
|
Subtarget->isFP64bit()))
|
|
getTargetStreamer().emitDirectiveModuleFP();
|
|
|
|
// We should always emit a '.module [no]oddspreg' but binutils 2.24 does not
|
|
// accept it. We therefore emit it when it contradicts the default or an
|
|
// option has changed the default (i.e. FPXX) and omit it otherwise.
|
|
if (Subtarget->isABI_O32() && (!Subtarget->useOddSPReg() ||
|
|
Subtarget->isABI_FPXX()))
|
|
getTargetStreamer().emitDirectiveModuleOddSPReg(Subtarget->useOddSPReg(),
|
|
Subtarget->isABI_O32());
|
|
}
|
|
|
|
void MipsAsmPrinter::EmitJal(MCSymbol *Symbol) {
|
|
MCInst I;
|
|
I.setOpcode(Mips::JAL);
|
|
I.addOperand(
|
|
MCOperand::CreateExpr(MCSymbolRefExpr::Create(Symbol, OutContext)));
|
|
OutStreamer.EmitInstruction(I, getSubtargetInfo());
|
|
}
|
|
|
|
void MipsAsmPrinter::EmitInstrReg(unsigned Opcode, unsigned Reg) {
|
|
MCInst I;
|
|
I.setOpcode(Opcode);
|
|
I.addOperand(MCOperand::CreateReg(Reg));
|
|
OutStreamer.EmitInstruction(I, getSubtargetInfo());
|
|
}
|
|
|
|
void MipsAsmPrinter::EmitInstrRegReg(unsigned Opcode, unsigned Reg1,
|
|
unsigned Reg2) {
|
|
MCInst I;
|
|
//
|
|
// Because of the current td files for Mips32, the operands for MTC1
|
|
// appear backwards from their normal assembly order. It's not a trivial
|
|
// change to fix this in the td file so we adjust for it here.
|
|
//
|
|
if (Opcode == Mips::MTC1) {
|
|
unsigned Temp = Reg1;
|
|
Reg1 = Reg2;
|
|
Reg2 = Temp;
|
|
}
|
|
I.setOpcode(Opcode);
|
|
I.addOperand(MCOperand::CreateReg(Reg1));
|
|
I.addOperand(MCOperand::CreateReg(Reg2));
|
|
OutStreamer.EmitInstruction(I, getSubtargetInfo());
|
|
}
|
|
|
|
void MipsAsmPrinter::EmitInstrRegRegReg(unsigned Opcode, unsigned Reg1,
|
|
unsigned Reg2, unsigned Reg3) {
|
|
MCInst I;
|
|
I.setOpcode(Opcode);
|
|
I.addOperand(MCOperand::CreateReg(Reg1));
|
|
I.addOperand(MCOperand::CreateReg(Reg2));
|
|
I.addOperand(MCOperand::CreateReg(Reg3));
|
|
OutStreamer.EmitInstruction(I, getSubtargetInfo());
|
|
}
|
|
|
|
void MipsAsmPrinter::EmitMovFPIntPair(unsigned MovOpc, unsigned Reg1,
|
|
unsigned Reg2, unsigned FPReg1,
|
|
unsigned FPReg2, bool LE) {
|
|
if (!LE) {
|
|
unsigned temp = Reg1;
|
|
Reg1 = Reg2;
|
|
Reg2 = temp;
|
|
}
|
|
EmitInstrRegReg(MovOpc, Reg1, FPReg1);
|
|
EmitInstrRegReg(MovOpc, Reg2, FPReg2);
|
|
}
|
|
|
|
void MipsAsmPrinter::EmitSwapFPIntParams(Mips16HardFloatInfo::FPParamVariant PV,
|
|
bool LE, bool ToFP) {
|
|
using namespace Mips16HardFloatInfo;
|
|
unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
|
|
switch (PV) {
|
|
case FSig:
|
|
EmitInstrRegReg(MovOpc, Mips::A0, Mips::F12);
|
|
break;
|
|
case FFSig:
|
|
EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);
|
|
break;
|
|
case FDSig:
|
|
EmitInstrRegReg(MovOpc, Mips::A0, Mips::F12);
|
|
EmitMovFPIntPair(MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
|
|
break;
|
|
case DSig:
|
|
EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
|
|
break;
|
|
case DDSig:
|
|
EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
|
|
EmitMovFPIntPair(MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
|
|
break;
|
|
case DFSig:
|
|
EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
|
|
EmitInstrRegReg(MovOpc, Mips::A2, Mips::F14);
|
|
break;
|
|
case NoSig:
|
|
return;
|
|
}
|
|
}
|
|
|
|
void
|
|
MipsAsmPrinter::EmitSwapFPIntRetval(Mips16HardFloatInfo::FPReturnVariant RV,
|
|
bool LE) {
|
|
using namespace Mips16HardFloatInfo;
|
|
unsigned MovOpc = Mips::MFC1;
|
|
switch (RV) {
|
|
case FRet:
|
|
EmitInstrRegReg(MovOpc, Mips::V0, Mips::F0);
|
|
break;
|
|
case DRet:
|
|
EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
|
|
break;
|
|
case CFRet:
|
|
EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
|
|
break;
|
|
case CDRet:
|
|
EmitMovFPIntPair(MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
|
|
EmitMovFPIntPair(MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);
|
|
break;
|
|
case NoFPRet:
|
|
break;
|
|
}
|
|
}
|
|
|
|
void MipsAsmPrinter::EmitFPCallStub(
|
|
const char *Symbol, const Mips16HardFloatInfo::FuncSignature *Signature) {
|
|
MCSymbol *MSymbol = OutContext.GetOrCreateSymbol(StringRef(Symbol));
|
|
using namespace Mips16HardFloatInfo;
|
|
bool LE = Subtarget->isLittle();
|
|
//
|
|
// .global xxxx
|
|
//
|
|
OutStreamer.EmitSymbolAttribute(MSymbol, MCSA_Global);
|
|
const char *RetType;
|
|
//
|
|
// make the comment field identifying the return and parameter
|
|
// types of the floating point stub
|
|
// # Stub function to call rettype xxxx (params)
|
|
//
|
|
switch (Signature->RetSig) {
|
|
case FRet:
|
|
RetType = "float";
|
|
break;
|
|
case DRet:
|
|
RetType = "double";
|
|
break;
|
|
case CFRet:
|
|
RetType = "complex";
|
|
break;
|
|
case CDRet:
|
|
RetType = "double complex";
|
|
break;
|
|
case NoFPRet:
|
|
RetType = "";
|
|
break;
|
|
}
|
|
const char *Parms;
|
|
switch (Signature->ParamSig) {
|
|
case FSig:
|
|
Parms = "float";
|
|
break;
|
|
case FFSig:
|
|
Parms = "float, float";
|
|
break;
|
|
case FDSig:
|
|
Parms = "float, double";
|
|
break;
|
|
case DSig:
|
|
Parms = "double";
|
|
break;
|
|
case DDSig:
|
|
Parms = "double, double";
|
|
break;
|
|
case DFSig:
|
|
Parms = "double, float";
|
|
break;
|
|
case NoSig:
|
|
Parms = "";
|
|
break;
|
|
}
|
|
OutStreamer.AddComment("\t# Stub function to call " + Twine(RetType) + " " +
|
|
Twine(Symbol) + " (" + Twine(Parms) + ")");
|
|
//
|
|
// probably not necessary but we save and restore the current section state
|
|
//
|
|
OutStreamer.PushSection();
|
|
//
|
|
// .section mips16.call.fpxxxx,"ax",@progbits
|
|
//
|
|
const MCSectionELF *M = OutContext.getELFSection(
|
|
".mips16.call.fp." + std::string(Symbol), ELF::SHT_PROGBITS,
|
|
ELF::SHF_ALLOC | ELF::SHF_EXECINSTR, SectionKind::getText());
|
|
OutStreamer.SwitchSection(M, nullptr);
|
|
//
|
|
// .align 2
|
|
//
|
|
OutStreamer.EmitValueToAlignment(4);
|
|
MipsTargetStreamer &TS = getTargetStreamer();
|
|
//
|
|
// .set nomips16
|
|
// .set nomicromips
|
|
//
|
|
TS.emitDirectiveSetNoMips16();
|
|
TS.emitDirectiveSetNoMicroMips();
|
|
//
|
|
// .ent __call_stub_fp_xxxx
|
|
// .type __call_stub_fp_xxxx,@function
|
|
// __call_stub_fp_xxxx:
|
|
//
|
|
std::string x = "__call_stub_fp_" + std::string(Symbol);
|
|
MCSymbol *Stub = OutContext.GetOrCreateSymbol(StringRef(x));
|
|
TS.emitDirectiveEnt(*Stub);
|
|
MCSymbol *MType =
|
|
OutContext.GetOrCreateSymbol("__call_stub_fp_" + Twine(Symbol));
|
|
OutStreamer.EmitSymbolAttribute(MType, MCSA_ELF_TypeFunction);
|
|
OutStreamer.EmitLabel(Stub);
|
|
//
|
|
// we just handle non pic for now. these function will not be
|
|
// called otherwise. when the full stub generation is moved here
|
|
// we need to deal with pic.
|
|
//
|
|
if (Subtarget->getRelocationModel() == Reloc::PIC_)
|
|
llvm_unreachable("should not be here if we are compiling pic");
|
|
TS.emitDirectiveSetReorder();
|
|
//
|
|
// We need to add a MipsMCExpr class to MCTargetDesc to fully implement
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// stubs without raw text but this current patch is for compiler generated
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// functions and they all return some value.
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// The calling sequence for non pic is different in that case and we need
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// to implement %lo and %hi in order to handle the case of no return value
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// See the corresponding method in Mips16HardFloat for details.
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//
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// mov the return address to S2.
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// we have no stack space to store it and we are about to make another call.
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// We need to make sure that the enclosing function knows to save S2
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// This should have already been handled.
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//
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// Mov $18, $31
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|
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EmitInstrRegRegReg(Mips::ADDu, Mips::S2, Mips::RA, Mips::ZERO);
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|
|
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EmitSwapFPIntParams(Signature->ParamSig, LE, true);
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|
|
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// Jal xxxx
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//
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EmitJal(MSymbol);
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|
|
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// fix return values
|
|
EmitSwapFPIntRetval(Signature->RetSig, LE);
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|
//
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// do the return
|
|
// if (Signature->RetSig == NoFPRet)
|
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// llvm_unreachable("should not be any stubs here with no return value");
|
|
// else
|
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EmitInstrReg(Mips::JR, Mips::S2);
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|
|
|
MCSymbol *Tmp = OutContext.CreateTempSymbol();
|
|
OutStreamer.EmitLabel(Tmp);
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const MCSymbolRefExpr *E = MCSymbolRefExpr::Create(Stub, OutContext);
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const MCSymbolRefExpr *T = MCSymbolRefExpr::Create(Tmp, OutContext);
|
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const MCExpr *T_min_E = MCBinaryExpr::CreateSub(T, E, OutContext);
|
|
OutStreamer.EmitELFSize(Stub, T_min_E);
|
|
TS.emitDirectiveEnd(x);
|
|
OutStreamer.PopSection();
|
|
}
|
|
|
|
void MipsAsmPrinter::EmitEndOfAsmFile(Module &M) {
|
|
// Emit needed stubs
|
|
//
|
|
for (std::map<
|
|
const char *,
|
|
const llvm::Mips16HardFloatInfo::FuncSignature *>::const_iterator
|
|
it = StubsNeeded.begin();
|
|
it != StubsNeeded.end(); ++it) {
|
|
const char *Symbol = it->first;
|
|
const llvm::Mips16HardFloatInfo::FuncSignature *Signature = it->second;
|
|
EmitFPCallStub(Symbol, Signature);
|
|
}
|
|
// return to the text section
|
|
OutStreamer.SwitchSection(OutContext.getObjectFileInfo()->getTextSection());
|
|
}
|
|
|
|
void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
|
|
raw_ostream &OS) {
|
|
// TODO: implement
|
|
}
|
|
|
|
// Align all targets of indirect branches on bundle size. Used only if target
|
|
// is NaCl.
|
|
void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) {
|
|
// Align all blocks that are jumped to through jump table.
|
|
if (MachineJumpTableInfo *JtInfo = MF.getJumpTableInfo()) {
|
|
const std::vector<MachineJumpTableEntry> &JT = JtInfo->getJumpTables();
|
|
for (unsigned I = 0; I < JT.size(); ++I) {
|
|
const std::vector<MachineBasicBlock*> &MBBs = JT[I].MBBs;
|
|
|
|
for (unsigned J = 0; J < MBBs.size(); ++J)
|
|
MBBs[J]->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
|
|
}
|
|
}
|
|
|
|
// If basic block address is taken, block can be target of indirect branch.
|
|
for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
|
|
MBB != E; ++MBB) {
|
|
if (MBB->hasAddressTaken())
|
|
MBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
|
|
}
|
|
}
|
|
|
|
bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const {
|
|
return (Opcode == Mips::LONG_BRANCH_LUi
|
|
|| Opcode == Mips::LONG_BRANCH_ADDiu
|
|
|| Opcode == Mips::LONG_BRANCH_DADDiu);
|
|
}
|
|
|
|
// Force static initialization.
|
|
extern "C" void LLVMInitializeMipsAsmPrinter() {
|
|
RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget);
|
|
RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget);
|
|
RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target);
|
|
RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget);
|
|
}
|