mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
ddbc274169
I followed three heuristics for deciding whether to set 'true' or 'false': - Everything target independent got 'true' as that is the expected common output of the GCC builtins. - If the target arch only has one way of implementing this operation, set the flag in the way that exercises the most of codegen. For most architectures this is also the likely path from a GCC builtin, with 'true' being set. It will (eventually) require lowering away that difference, and then lowering to the architecture's operation. - Otherwise, set the flag differently dependending on which target operation should be tested. Let me know if anyone has any issue with this pattern or would like specific tests of another form. This should allow the x86 codegen to just iteratively improve as I teach the backend how to differentiate between the two forms, and everything else should remain exactly the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146370 91177308-0d34-0410-b5e6-96231b3b80d8
187 lines
4.2 KiB
LLVM
187 lines
4.2 KiB
LLVM
; RUN: opt < %s -instcombine -S | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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declare i32 @llvm.ctpop.i32(i32)
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declare i32 @llvm.ctlz.i32(i32, i1)
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declare i32 @llvm.cttz.i32(i32, i1)
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define i64 @test1(i32 %x) {
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%t = call i32 @llvm.ctpop.i32(i32 %x)
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%s = sext i32 %t to i64
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ret i64 %s
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; CHECK: @test1
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; CHECK: zext i32 %t
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}
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define i64 @test2(i32 %x) {
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%t = call i32 @llvm.ctlz.i32(i32 %x, i1 true)
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%s = sext i32 %t to i64
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ret i64 %s
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; CHECK: @test2
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; CHECK: zext i32 %t
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}
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define i64 @test3(i32 %x) {
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%t = call i32 @llvm.cttz.i32(i32 %x, i1 true)
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%s = sext i32 %t to i64
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ret i64 %s
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; CHECK: @test3
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; CHECK: zext i32 %t
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}
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define i64 @test4(i32 %x) {
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%t = udiv i32 %x, 3
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%s = sext i32 %t to i64
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ret i64 %s
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; CHECK: @test4
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; CHECK: zext i32 %t
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}
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define i64 @test5(i32 %x) {
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%t = urem i32 %x, 30000
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%s = sext i32 %t to i64
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ret i64 %s
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; CHECK: @test5
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; CHECK: zext i32 %t
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}
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define i64 @test6(i32 %x) {
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%u = lshr i32 %x, 3
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%t = mul i32 %u, 3
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%s = sext i32 %t to i64
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ret i64 %s
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; CHECK: @test6
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; CHECK: zext i32 %t
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}
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define i64 @test7(i32 %x) {
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%t = and i32 %x, 511
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%u = sub i32 20000, %t
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%s = sext i32 %u to i64
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ret i64 %s
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; CHECK: @test7
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; CHECK: zext i32 %u to i64
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}
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define i32 @test8(i8 %a, i32 %f, i1 %p, i32* %z) {
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%d = lshr i32 %f, 24
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%e = select i1 %p, i32 %d, i32 0
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%s = trunc i32 %e to i16
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%n = sext i16 %s to i32
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ret i32 %n
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; CHECK: @test8
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; CHECK: %d = lshr i32 %f, 24
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; CHECK: %n = select i1 %p, i32 %d, i32 0
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; CHECK: ret i32 %n
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}
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; rdar://6013816
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define i16 @test9(i16 %t, i1 %cond) nounwind {
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entry:
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br i1 %cond, label %T, label %F
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T:
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%t2 = sext i16 %t to i32
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br label %F
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F:
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%V = phi i32 [%t2, %T], [42, %entry]
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%W = trunc i32 %V to i16
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ret i16 %W
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; CHECK: @test9
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; CHECK: T:
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; CHECK-NEXT: br label %F
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; CHECK: F:
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; CHECK-NEXT: phi i16
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; CHECK-NEXT: ret i16
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}
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; PR2638
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define i32 @test10(i32 %i) nounwind {
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entry:
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%tmp12 = trunc i32 %i to i8
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%tmp16 = shl i8 %tmp12, 6
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%a = ashr i8 %tmp16, 6
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%b = sext i8 %a to i32
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ret i32 %b
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; CHECK: @test10
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; CHECK: shl i32 %i, 30
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; CHECK-NEXT: ashr exact i32
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; CHECK-NEXT: ret i32
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}
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define void @test11(<2 x i16> %srcA, <2 x i16> %srcB, <2 x i16>* %dst) {
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%cmp = icmp eq <2 x i16> %srcB, %srcA
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%sext = sext <2 x i1> %cmp to <2 x i16>
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%tmask = ashr <2 x i16> %sext, <i16 15, i16 15>
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store <2 x i16> %tmask, <2 x i16>* %dst
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ret void
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; CHECK: @test11
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; CHECK-NEXT: icmp eq
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; CHECK-NEXT: sext <2 x i1>
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; CHECK-NEXT: store <2 x i16>
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; CHECK-NEXT: ret
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}
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define i64 @test12(i32 %x) nounwind {
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%shr = lshr i32 %x, 1
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%sub = sub nsw i32 0, %shr
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%conv = sext i32 %sub to i64
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ret i64 %conv
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; CHECK: @test12
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; CHECK: sext
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; CHECK: ret
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}
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define i32 @test13(i32 %x) nounwind {
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%and = and i32 %x, 8
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%cmp = icmp eq i32 %and, 0
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%ext = sext i1 %cmp to i32
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ret i32 %ext
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; CHECK: @test13
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; CHECK-NEXT: %and = lshr i32 %x, 3
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; CHECK-NEXT: %1 = and i32 %and, 1
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; CHECK-NEXT: %sext = add i32 %1, -1
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; CHECK-NEXT: ret i32 %sext
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}
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define i32 @test14(i16 %x) nounwind {
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%and = and i16 %x, 16
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%cmp = icmp ne i16 %and, 16
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%ext = sext i1 %cmp to i32
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ret i32 %ext
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; CHECK: @test14
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; CHECK-NEXT: %and = lshr i16 %x, 4
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; CHECK-NEXT: %1 = and i16 %and, 1
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; CHECK-NEXT: %sext = add i16 %1, -1
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; CHECK-NEXT: %ext = sext i16 %sext to i32
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; CHECK-NEXT: ret i32 %ext
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}
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define i32 @test15(i32 %x) nounwind {
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%and = and i32 %x, 16
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%cmp = icmp ne i32 %and, 0
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%ext = sext i1 %cmp to i32
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ret i32 %ext
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; CHECK: @test15
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; CHECK-NEXT: %1 = shl i32 %x, 27
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; CHECK-NEXT: %sext = ashr i32 %1, 31
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; CHECK-NEXT: ret i32 %sext
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}
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define i32 @test16(i16 %x) nounwind {
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%and = and i16 %x, 8
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%cmp = icmp eq i16 %and, 8
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%ext = sext i1 %cmp to i32
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ret i32 %ext
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; CHECK: @test16
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; CHECK-NEXT: %1 = shl i16 %x, 12
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; CHECK-NEXT: %sext = ashr i16 %1, 15
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; CHECK-NEXT: %ext = sext i16 %sext to i32
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; CHECK-NEXT: ret i32 %ext
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}
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