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And add Sandybridge/Haswell resource buffers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184034 91177308-0d34-0410-b5e6-96231b3b80d8
409 lines
14 KiB
C++
409 lines
14 KiB
C++
//===- CodeGenSchedule.h - Scheduling Machine Models ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines structures to encapsulate the machine model as decribed in
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// the target description.
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//
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//===----------------------------------------------------------------------===//
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#ifndef CODEGEN_SCHEDULE_H
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#define CODEGEN_SCHEDULE_H
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#include "SetTheory.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/StringMap.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/TableGen/Record.h"
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namespace llvm {
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class CodeGenTarget;
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class CodeGenSchedModels;
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class CodeGenInstruction;
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typedef std::vector<Record*> RecVec;
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typedef std::vector<Record*>::const_iterator RecIter;
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typedef std::vector<unsigned> IdxVec;
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typedef std::vector<unsigned>::const_iterator IdxIter;
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void splitSchedReadWrites(const RecVec &RWDefs,
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RecVec &WriteDefs, RecVec &ReadDefs);
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/// We have two kinds of SchedReadWrites. Explicitly defined and inferred
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/// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or
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/// may not be empty. TheDef is null for inferred sequences, and Sequence must
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/// be nonempty.
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///
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/// IsVariadic controls whether the variants are expanded into multiple operands
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/// or a sequence of writes on one operand.
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struct CodeGenSchedRW {
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unsigned Index;
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std::string Name;
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Record *TheDef;
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bool IsRead;
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bool IsAlias;
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bool HasVariants;
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bool IsVariadic;
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bool IsSequence;
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IdxVec Sequence;
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RecVec Aliases;
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CodeGenSchedRW()
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: Index(0), TheDef(0), IsRead(false), IsAlias(false),
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HasVariants(false), IsVariadic(false), IsSequence(false) {}
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CodeGenSchedRW(unsigned Idx, Record *Def)
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: Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) {
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Name = Def->getName();
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IsRead = Def->isSubClassOf("SchedRead");
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HasVariants = Def->isSubClassOf("SchedVariant");
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if (HasVariants)
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IsVariadic = Def->getValueAsBit("Variadic");
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// Read records don't currently have sequences, but it can be easily
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// added. Note that implicit Reads (from ReadVariant) may have a Sequence
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// (but no record).
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IsSequence = Def->isSubClassOf("WriteSequence");
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}
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CodeGenSchedRW(unsigned Idx, bool Read, const IdxVec &Seq,
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const std::string &Name)
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: Index(Idx), Name(Name), TheDef(0), IsRead(Read), IsAlias(false),
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HasVariants(false), IsVariadic(false), IsSequence(true), Sequence(Seq) {
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assert(Sequence.size() > 1 && "implied sequence needs >1 RWs");
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}
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bool isValid() const {
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assert((!HasVariants || TheDef) && "Variant write needs record def");
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assert((!IsVariadic || HasVariants) && "Variadic write needs variants");
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assert((!IsSequence || !HasVariants) && "Sequence can't have variant");
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assert((!IsSequence || !Sequence.empty()) && "Sequence should be nonempty");
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assert((!IsAlias || Aliases.empty()) && "Alias cannot have aliases");
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return TheDef || !Sequence.empty();
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}
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#ifndef NDEBUG
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void dump() const;
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#endif
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};
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/// Represent a transition between SchedClasses induced by SchedVariant.
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struct CodeGenSchedTransition {
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unsigned ToClassIdx;
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IdxVec ProcIndices;
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RecVec PredTerm;
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};
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/// Scheduling class.
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///
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/// Each instruction description will be mapped to a scheduling class. There are
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/// four types of classes:
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///
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/// 1) An explicitly defined itinerary class with ItinClassDef set.
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/// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor.
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///
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/// 2) An implied class with a list of SchedWrites and SchedReads that are
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/// defined in an instruction definition and which are common across all
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/// subtargets. ProcIndices contains 0 for any processor.
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///
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/// 3) An implied class with a list of InstRW records that map instructions to
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/// SchedWrites and SchedReads per-processor. InstrClassMap should map the same
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/// instructions to this class. ProcIndices contains all the processors that
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/// provided InstrRW records for this class. ItinClassDef or Writes/Reads may
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/// still be defined for processors with no InstRW entry.
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///
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/// 4) An inferred class represents a variant of another class that may be
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/// resolved at runtime. ProcIndices contains the set of processors that may
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/// require the class. ProcIndices are propagated through SchedClasses as
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/// variants are expanded. Multiple SchedClasses may be inferred from an
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/// itinerary class. Each inherits the processor index from the ItinRW record
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/// that mapped the itinerary class to the variant Writes or Reads.
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struct CodeGenSchedClass {
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unsigned Index;
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std::string Name;
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Record *ItinClassDef;
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IdxVec Writes;
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IdxVec Reads;
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// Sorted list of ProcIdx, where ProcIdx==0 implies any processor.
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IdxVec ProcIndices;
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std::vector<CodeGenSchedTransition> Transitions;
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// InstRW records associated with this class. These records may refer to an
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// Instruction no longer mapped to this class by InstrClassMap. These
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// Instructions should be ignored by this class because they have been split
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// off to join another inferred class.
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RecVec InstRWs;
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CodeGenSchedClass(): Index(0), ItinClassDef(0) {}
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bool isKeyEqual(Record *IC, const IdxVec &W, const IdxVec &R) {
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return ItinClassDef == IC && Writes == W && Reads == R;
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}
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// Is this class generated from a variants if existing classes? Instructions
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// are never mapped directly to inferred scheduling classes.
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bool isInferred() const { return !ItinClassDef; }
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#ifndef NDEBUG
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void dump(const CodeGenSchedModels *SchedModels) const;
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#endif
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};
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// Processor model.
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//
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// ModelName is a unique name used to name an instantiation of MCSchedModel.
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//
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// ModelDef is NULL for inferred Models. This happens when a processor defines
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// an itinerary but no machine model. If the processer defines neither a machine
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// model nor itinerary, then ModelDef remains pointing to NoModel. NoModel has
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// the special "NoModel" field set to true.
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//
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// ItinsDef always points to a valid record definition, but may point to the
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// default NoItineraries. NoItineraries has an empty list of InstrItinData
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// records.
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//
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// ItinDefList orders this processor's InstrItinData records by SchedClass idx.
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struct CodeGenProcModel {
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unsigned Index;
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std::string ModelName;
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Record *ModelDef;
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Record *ItinsDef;
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// Derived members...
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// Array of InstrItinData records indexed by a CodeGenSchedClass index.
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// This list is empty if the Processor has no value for Itineraries.
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// Initialized by collectProcItins().
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RecVec ItinDefList;
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// Map itinerary classes to per-operand resources.
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// This list is empty if no ItinRW refers to this Processor.
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RecVec ItinRWDefs;
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// All read/write resources associated with this processor.
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RecVec WriteResDefs;
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RecVec ReadAdvanceDefs;
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// Per-operand machine model resources associated with this processor.
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RecVec ProcResourceDefs;
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RecVec ProcResGroupDefs;
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CodeGenProcModel(unsigned Idx, const std::string &Name, Record *MDef,
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Record *IDef) :
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Index(Idx), ModelName(Name), ModelDef(MDef), ItinsDef(IDef) {}
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bool hasItineraries() const {
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return !ItinsDef->getValueAsListOfDefs("IID").empty();
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}
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bool hasInstrSchedModel() const {
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return !WriteResDefs.empty() || !ItinRWDefs.empty();
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}
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unsigned getProcResourceIdx(Record *PRDef) const;
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#ifndef NDEBUG
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void dump() const;
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#endif
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};
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/// Top level container for machine model data.
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class CodeGenSchedModels {
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RecordKeeper &Records;
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const CodeGenTarget &Target;
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// Map dag expressions to Instruction lists.
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SetTheory Sets;
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// List of unique processor models.
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std::vector<CodeGenProcModel> ProcModels;
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// Map Processor's MachineModel or ProcItin to a CodeGenProcModel index.
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typedef DenseMap<Record*, unsigned> ProcModelMapTy;
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ProcModelMapTy ProcModelMap;
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// Per-operand SchedReadWrite types.
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std::vector<CodeGenSchedRW> SchedWrites;
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std::vector<CodeGenSchedRW> SchedReads;
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// List of unique SchedClasses.
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std::vector<CodeGenSchedClass> SchedClasses;
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// Any inferred SchedClass has an index greater than NumInstrSchedClassses.
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unsigned NumInstrSchedClasses;
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// Map each instruction to its unique SchedClass index considering the
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// combination of it's itinerary class, SchedRW list, and InstRW records.
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typedef DenseMap<Record*, unsigned> InstClassMapTy;
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InstClassMapTy InstrClassMap;
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public:
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CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT);
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Record *getModelOrItinDef(Record *ProcDef) const {
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Record *ModelDef = ProcDef->getValueAsDef("SchedModel");
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Record *ItinsDef = ProcDef->getValueAsDef("ProcItin");
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if (!ItinsDef->getValueAsListOfDefs("IID").empty()) {
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assert(ModelDef->getValueAsBit("NoModel")
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&& "Itineraries must be defined within SchedMachineModel");
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return ItinsDef;
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}
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return ModelDef;
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}
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const CodeGenProcModel &getModelForProc(Record *ProcDef) const {
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Record *ModelDef = getModelOrItinDef(ProcDef);
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ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
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assert(I != ProcModelMap.end() && "missing machine model");
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return ProcModels[I->second];
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}
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CodeGenProcModel &getProcModel(Record *ModelDef) {
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ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
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assert(I != ProcModelMap.end() && "missing machine model");
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return ProcModels[I->second];
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}
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const CodeGenProcModel &getProcModel(Record *ModelDef) const {
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return const_cast<CodeGenSchedModels*>(this)->getProcModel(ModelDef);
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}
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// Iterate over the unique processor models.
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typedef std::vector<CodeGenProcModel>::const_iterator ProcIter;
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ProcIter procModelBegin() const { return ProcModels.begin(); }
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ProcIter procModelEnd() const { return ProcModels.end(); }
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// Return true if any processors have itineraries.
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bool hasItineraries() const;
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// Get a SchedWrite from its index.
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const CodeGenSchedRW &getSchedWrite(unsigned Idx) const {
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assert(Idx < SchedWrites.size() && "bad SchedWrite index");
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assert(SchedWrites[Idx].isValid() && "invalid SchedWrite");
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return SchedWrites[Idx];
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}
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// Get a SchedWrite from its index.
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const CodeGenSchedRW &getSchedRead(unsigned Idx) const {
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assert(Idx < SchedReads.size() && "bad SchedRead index");
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assert(SchedReads[Idx].isValid() && "invalid SchedRead");
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return SchedReads[Idx];
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}
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const CodeGenSchedRW &getSchedRW(unsigned Idx, bool IsRead) const {
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return IsRead ? getSchedRead(Idx) : getSchedWrite(Idx);
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}
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CodeGenSchedRW &getSchedRW(Record *Def) {
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bool IsRead = Def->isSubClassOf("SchedRead");
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unsigned Idx = getSchedRWIdx(Def, IsRead);
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return const_cast<CodeGenSchedRW&>(
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IsRead ? getSchedRead(Idx) : getSchedWrite(Idx));
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}
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const CodeGenSchedRW &getSchedRW(Record*Def) const {
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return const_cast<CodeGenSchedModels&>(*this).getSchedRW(Def);
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}
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unsigned getSchedRWIdx(Record *Def, bool IsRead, unsigned After = 0) const;
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// Return true if the given write record is referenced by a ReadAdvance.
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bool hasReadOfWrite(Record *WriteDef) const;
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// Get a SchedClass from its index.
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CodeGenSchedClass &getSchedClass(unsigned Idx) {
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assert(Idx < SchedClasses.size() && "bad SchedClass index");
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return SchedClasses[Idx];
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}
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const CodeGenSchedClass &getSchedClass(unsigned Idx) const {
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assert(Idx < SchedClasses.size() && "bad SchedClass index");
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return SchedClasses[Idx];
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}
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// Get the SchedClass index for an instruction. Instructions with no
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// itinerary, no SchedReadWrites, and no InstrReadWrites references return 0
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// for NoItinerary.
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unsigned getSchedClassIdx(const CodeGenInstruction &Inst) const;
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typedef std::vector<CodeGenSchedClass>::const_iterator SchedClassIter;
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SchedClassIter schedClassBegin() const { return SchedClasses.begin(); }
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SchedClassIter schedClassEnd() const { return SchedClasses.end(); }
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unsigned numInstrSchedClasses() const { return NumInstrSchedClasses; }
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void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
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void findRWs(const RecVec &RWDefs, IdxVec &RWs, bool IsRead) const;
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void expandRWSequence(unsigned RWIdx, IdxVec &RWSeq, bool IsRead) const;
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void expandRWSeqForProc(unsigned RWIdx, IdxVec &RWSeq, bool IsRead,
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const CodeGenProcModel &ProcModel) const;
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unsigned addSchedClass(Record *ItinDef, const IdxVec &OperWrites,
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const IdxVec &OperReads, const IdxVec &ProcIndices);
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unsigned findOrInsertRW(ArrayRef<unsigned> Seq, bool IsRead);
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unsigned findSchedClassIdx(Record *ItinClassDef,
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const IdxVec &Writes,
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const IdxVec &Reads) const;
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Record *findProcResUnits(Record *ProcResKind,
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const CodeGenProcModel &PM) const;
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private:
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void collectProcModels();
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// Initialize a new processor model if it is unique.
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void addProcModel(Record *ProcDef);
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void collectSchedRW();
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std::string genRWName(const IdxVec& Seq, bool IsRead);
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unsigned findRWForSequence(const IdxVec &Seq, bool IsRead);
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void collectSchedClasses();
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std::string createSchedClassName(Record *ItinClassDef,
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const IdxVec &OperWrites,
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const IdxVec &OperReads);
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std::string createSchedClassName(const RecVec &InstDefs);
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void createInstRWClass(Record *InstRWDef);
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void collectProcItins();
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void collectProcItinRW();
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void inferSchedClasses();
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void inferFromRW(const IdxVec &OperWrites, const IdxVec &OperReads,
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unsigned FromClassIdx, const IdxVec &ProcIndices);
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void inferFromItinClass(Record *ItinClassDef, unsigned FromClassIdx);
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void inferFromInstRWs(unsigned SCIdx);
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bool hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM);
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void verifyProcResourceGroups(CodeGenProcModel &PM);
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void collectProcResources();
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void collectItinProcResources(Record *ItinClassDef);
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void collectRWResources(unsigned RWIdx, bool IsRead,
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const IdxVec &ProcIndices);
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void collectRWResources(const IdxVec &Writes, const IdxVec &Reads,
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const IdxVec &ProcIndices);
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void addProcResource(Record *ProcResourceKind, CodeGenProcModel &PM);
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void addWriteRes(Record *ProcWriteResDef, unsigned PIdx);
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void addReadAdvance(Record *ProcReadAdvanceDef, unsigned PIdx);
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};
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} // namespace llvm
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#endif
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